Package Mechanical Specifications and Pin Information
Signal Name
Type
Description
TDO (Test Data Out) transfers serial test data out of the
processor. TDO provides the serial output needed for JTAG
specification support. Please contact your Intel representative for
more implementation details.
TDO
O
Refer to the appropriate platform design guide for further TEST1,
TEST2, TEST3, and TEST4 termination requirements and
implementation details. All TEST signals can be left as No
Connects.
TEST[1:4]
The processor protects itself from catastrophic overheating by
use of an internal thermal sensor. This sensor is set well above
the normal operating temperature to ensure that there are no
false trips. The processor will stop all execution when the junction
temperature exceeds approximately 125°C. This condition is
signaled to the system by the THERMTRIP# (Thermal Trip) pin.
For termination requirements, please contact your Intel
representative for more implementation details.
THRMTRIP#
O
THRMDA
THRMDC
PWR
PWR
Thermal Diode - Anode
Thermal Diode - Cathode
TMS (Test Mode Select) is a JTAG specification support signal
used by debug tools. Please contact your Intel representative for
more implementation details.
TMS
I
TRDY# (Target Ready) is asserted by the target to indicate that it
is ready to receive a write or implicit writeback data transfer.
TRDY# must connect the appropriate pins of both FSB agents.
TRDY#
TRST#
VCCA
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic.
TRST# must be driven low during power on Reset. Please contact
your Intel representative for more implementation details.
VCCA provides isolated power for the internal processor core
PLLs. Please contact your Intel representative for more
implementation details.
PWR
VCC
VSS
PWR
GND
GND
Processor core power supply
Processor core ground node.
Non Critical to Function
VSS / NCTF
VID [6:0] (Voltage ID) pins are used to support automatic
selection of power supply voltages (VCC). Unlike some previous
generations of processors, these are CMOS signals that are
driven by the processor. The voltage supply for these pins must
be valid before the VR can supply VCC to the processor.
Conversely, the VR output must be disabled until the voltage
supply for the VID pins becomes valid. The VID pins are needed
to support the processor voltage specification variations. See
Table 3 for definitions of these pins. The VR must supply the
voltage that is requested by the pins, or disable itself.
VID [6:0]
O
VCCP
PWR
Processor I/O Power Supply
48
Datasheet
INTEL [ INTEL ]
