Package Mechanical Specifications and Pin Information
Signal Name
Type
Description
Lock# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of
the last transaction.
LOCK#
I/O
When the priority agent asserts BPRI# to arbitrate for ownership
of the FSB, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the FSB
throughout the bus locked operation and ensure the atomicity of
lock.
Probe Ready signal used by debug tools to request debug
operation of the processor. Please contact your Intel
representative for more implementation details.
PRDY#
PREQ#
O
I
Probe Request signal used by debug tools to request debug
operation of the processor. Please contact your Intel
representative for more implementation details.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit (TCC)
has been activated, if enabled. As an input, assertion of
I/O, O
(DP)
PROCHOT#
PROCHOT# by the system will activate the TCC, if enabled. The
TCC will remain active until the system de-asserts PROCHOT#.
This signal may require voltage translation on the motherboard.
Please contact your Intel representative for more implementation
details.
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD
can be driven inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification, and be
followed by a 2-ms (minimum) RESET# pulse.
PWRGOOD
I
The PWRGOOD signal must be supplied to the processor; it is
used to protect internal circuits against voltage sequencing
issues. It should be driven high throughout boundary scan
operation. For termination requirements, please contact your
Intel representative for more implementation details.
REQ [4:0]# (Request Command) must connect the appropriate
pins of both FSB agents. They are asserted by the current bus
owner to define the currently active transaction type. These
signals are source synchronous to ADSTB [0] #.
REQ [4:0]#
I/O
46
Datasheet
INTEL [ INTEL ]
