EPCS Device Memory Access
Page 27
Figure 16 shows the instruction sequence of the erase bulk operation.
Figure 16. Erase Bulk Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
DCLK
ASDI
Operation Code
Erase Sector Operation
The erase sector operation code is b'1101 1000and it lists the MSB first. This
operation allows you to erase a certain sector in the EPCS device by setting all the bits
inside the sector to or 0xFF. This operation is useful if you want to access the unused
1
sectors as general purpose memory in your applications. You must execute the write
enable operation before the erase sector operation so that the write enable latch bit in
the status register is set to 1.
You can implement the erase sector operation by first driving the nCSsignal low, then
you shift in the erase sector operation code, followed by the three address bytes of the
chosen sector on the ASDIpin. The three address bytes for the erase sector operation
can be any address inside the specified sector. For more information about the sector
address range, refer to Table 3 on page 7 through Table 7 on page 12. Drive the nCS
signal high after the eighth bit of the erase sector operation code has been latched in.
The device initiates the self-timed erase sector cycle immediately after the nCSsignal is
driven high. For more information about the self-timed erase sector cycle time, refer to
the tES value in Table 16 on page 29.
You must account for this delay before accessing the memory contents. Alternatively,
you can check the write in progress bit in the status register by executing the read
status operation while the self-timed erase sector cycle is in progress. The write in
progress bit is set to
1
during the self-timed erase sector cycle and
0
when it is
complete. The write enable latch bit in the status register resets to
cycle is complete.
0
before the erase
Figure 17 shows the instruction sequence of the erase sector operation.
Figure 17. Erase Sector Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
8
9
28 29 30 31
DCLK
ASDI
Operation Code
24-Bit Address (1)
23 22
3
2
1
0
MSB
Note to Figure 17:
(1) Address bit A[23]is a don't-care bit in the EPCS64 device. Address bits A[23..21]are don't-care bits in the EPCS16 device. Address bits
A[23..19]are don't-care bits in the EPCS4 device. Address bits A[23..17]are don't-care bits in the EPCS1 device.
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
