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EPCS Device Memory Access
Figure 13 shows the instruction sequence of the read silicon ID operation.
Figure 13. Read Silicon ID Operation Timing Diagram (1)
nCS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
DCLK
Operation Code
Three Dummy Bytes
23 22 21
MSB
3
2
1
0
ASDI
Silicon ID
High Impedance
7
6
5
4
3
2
1
0
DATA
MSB
Note to Figure 13:
(1) Only EPCS1, EPCS4, EPCS16, and EPCS64 devices support the read silicon ID operation.
Read Device Identification Operation
The read device identification operation code is b’1001 1111and it lists the MSB first.
Only EPCS128 device supports this operation. This operation reads the 8-bit device
identification of the EPCS device from the DATAoutput pin. If this operation is shifted
in during an erase or write cycle, it is ignored and does not affect the cycle that is in
progress. Table 15 lists the EPCS device identification.
Table 15. EPCS Device Identification
EPCS Device
Silicon ID (Binary Value)
EPCS128
b'0001 1000
The device implements the read device identification operation by driving the nCS
signal low and then shifting in the read device identification operation code, followed
by two dummy bytes on the ASDIpin. The 16-bit device identification of the EPCS
device is then shifted out on the DATApin on the falling edge of the DCLKsignal. The
device can terminate the read device identification operation by driving the nCSsignal
high after reading the device identification at least one time.
Figure 14 shows the instruction sequence of the read device identification operation.
Figure 14. Read Device Identification Operation Timing Diagram(1)
nCS
0
1
2
3
4
5
6
7
8
9
10
20 21 23 24 25 26 27 28 29 30 31 32
DCLK
Operation Code
Two Dummy Bytes
14
13
15
MSB
3
2
1
0
ASDI
Silicon ID
High Impedance
7
6
5
4
3
2
1
0
DATA
MSB
Note to Figure 14:
(1) Only EPCS128 device supports the read device identification operation.
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
