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Power and Operation
Power and Operation
This section describes the power modes, power-on reset (POR) delay, error detection,
and initial programming state of the EPCS devices.
Power Mode
EPCS devices support active and standby power modes. When the nCSsignal is low,
the device is enabled and is in active power mode. The FPGA is configured while the
EPCS device is in active power mode. When the nCSsignal is high, the device is
disabled but remains in active power mode until all internal cycles are completed,
such as write or erase operations. The EPCS device then goes into standby power
mode. The ICC1 and ICC0 parameters list the VCC supply current when the device is in
active and standby power modes. For more information, refer to Table 21 on page 34.
Power-On Reset
During the initial power-up, a POR delay occurs to ensure the system voltage levels
have stabilized. During the AS configuration, the FPGA controls the configuration
and has a longer POR delay than the EPCS device.
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For more information about the POR delay time, refer to the configuration chapter in
the appropriate device handbook.
Error Detection
During the AS configuration with the EPCS device, the FPGA monitors the
configuration status through the nSTATUSand CONF_DONEpins. If an error condition
occurs, if the nSTATUSpin drives low or if the CONF_DONEpin does not go high, the
FPGA begins reconfiguration by pulsing the nSTATUSand nCSOsignals, which controls
the chip select (nCS) pin on the EPCS device.
After an error, the configuration automatically restarts if the Auto-Restart Upon
Frame Error option is turned on in the Quartus II software. If the option is turned off,
the system must monitor the nSTATUSsignal for errors and then pulse the nCONFIG
signal low to restart configuration.
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
