Figure 15 shows the instruction sequence of the write bytes operation.
(1)
Figure 15. Write Bytes Operation Timing Diagram
nCS
DCLK
ASDI
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
2072 2073 2074 2075 2076 2077 2078 2079
Operation Code
24-Bit Address (2)
Data Byte 1
Data Byte 2
Data Byte 256
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB (3)
MSB (3)
MSB (3)
Notes to Figure 15:
(1) Use the erase sector operation or the erase bulk operation to initialize the memory bytes of the EPCS devices to all
1
or 0xFFbefore implementing the write bytes operation.
(2) Address bit A[23]is a don't-care bit in the EPCS64 device. Address bits A[23..21]are don't-care bits in the EPCS16 device. Address bits A[23..19]are don't-care bits in the EPCS4 device. Address
bits A[23..17]are don't-care bits in the EPCS1 device.
(3) For .rpd files, write the LSB of the data byte first.
Erase Bulk Operation
The erase bulk operation code is b'1100 0111and it lists the MSB first. This operation sets all the memory bits to
Similar to the write bytes operation, you must execute the write enable operation before the erase bulk operation so that the
write enable latch bit in the status register is set to
1or 0xFF.
1.
You can implement the erase bulk operation by driving the nCSsignal low and then shifting in the erase bulk operation code on
the ASDIpin. The nCSsignal must be driven high after the eighth bit of the erase bulk operation code has been latched in.
The device initiates a self-timed erase bulk cycle immediately after the nCSsignal is driven high. For more information about
the self-timed erase bulk cycle time, refer to the tEB value in Table 16 on page 29.
You must account for this delay before accessing the memory contents. Alternatively, you can check the write in progress bit in
the status register by executing the read status operation while the self-timed erase cycle is in progress. The write in progress
bit is set to
1during the self-timed erase cycle and 0when it is complete. The write enable latch bit in the status register is reset
to before the erase cycle is complete.
0
INTEL [ INTEL ]
