Timing Information
Page 31
Figure 20 shows the timing waveform for the AS configuration scheme of the FPGA
using an EPCS device.
Figure 20. AS Configuration Timing Diagram
tCF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
Read Address
ASDO
DATA0
bit
N
bit N-1
bit
1
bit 0
t
(1)
CD2UM
INIT_DONE
User I/O
User Mode
Tri-stated with internal pull-up resistor
Note to Figure 20:
(1) tCD2UM is an FPGA-dependent parameter. For more information, refer to the configuration chapter in the appropriate device handbook.
f
For more information about the timing parameters in Figure 20, refer to the
configuration chapter in the appropriate device handbook.
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
