Timing Information
Page 29
Timing Information
Figure 18 shows the timing waveform for the write operation of the EPCS device.
Figure 18. Write Operation Timing Diagram
t
CSH
nCS
t
t
t
t
CL
NCSH
NCSSU
CH
DCLK
ASDI
DATA
t
t
DH
DSU
Bit n
Bit n 1
Bit 0
High Impedance
Table 16 lists the EPCS device timing parameters for the write operation.
Table 16. Write Operation Parameters
Symbol
Parameter
Min
Typ
Max
Unit
Write clock frequency (from the FPGA, download cable, or
embedded processor) for write enable, write disable, read status,
read silicon ID, write bytes, erase bulk, and erase sector
operations
fWCLK
—
—
25
MHz
tCH
DCLKhigh time
20
20
10
10
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tCL
DCLKlow time
tNCSSU
tNCSH
tDSU
tDH
Chip select (nCS) setup time
Chip select (nCS) hold time
Data (ASDI) in setup time before the rising edge on DCLK
Data (ASDI) hold time after rising edge on DCLK
Chip select (nCS) high time
5
tCSH
100
Write bytes cycle time for EPCS1, EPCS4, EPCS16, and EPCS64
devices
—
1.5
5
ms
(1)
tWB
Write bytes cycle time for the EPCS128 device
Write status cycle time
—
—
—
—
—
—
—
2.5
5
7
ms
ms
s
(1)
tWS
15
6
Erase bulk cycle time for the EPCS1 device
Erase bulk cycle time for the EPCS4 device
Erase bulk cycle time for the EPCS16 device
Erase bulk cycle time for the EPCS64 device
Erase bulk cycle time for the EPCS128 device
3
5
10
40
160
250
s
(1)
tEB
17
68
105
s
s
s
Erase sector cycle time for EPCS1, EPCS4, EPCS16, and EPCS64
devices
—
—
2
2
3
6
s
s
(1)
tES
Erase sector cycle time for the EPCS128 device
Note to Table 16:
(1) Figure 18 does not show these parameters.
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
