EPCS Device Memory Access
Page 23
Figure 12 shows the instruction sequence of the fast read operation.
Figure 12. Fast Read Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
DCLK
ASDI
Operation Code
24-Bit Address (1)
23 22 21
MSB
3
2
1
0
High Impedance
DATA
nCS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DCLK
ASDI
DATA
Dummy Byte
7
6
5
4
3
2
0
1
DATA Out 1
DATA Out 2
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
Note to Figure 12:
(1) Address bit A[23]is a don't-care bit in the EPCS64 device. Address bits A[23..21]are don't-care bits in the
EPCS16 device. Address bits A[23..19]are don't-care bits in the EPCS4 device. Address bits A[23..17]are
don't-care bits in the EPCS1 device.
Read Silicon ID Operation
The read silicon ID operation code is b'1010 1011and it lists the MSB first. Only
EPCS1, EPCS4, EPCS16, and EPCS64 devices support this operation. This operation
reads the 8-bit silicon ID of the EPCS device from the DATAoutput pin. If this operation
is shifted in during an erase or write cycle, it is ignored and does not affect the cycle
that is in progress.
Table 14 lists the EPCS device silicon IDs.
Table 14. EPCS Device Silicon ID
EPCS Device
EPCS1
Silicon ID (Binary Value)
b'0001 0000
b'0001 0010
b'0001 0100
b'0001 0110
EPCS4
EPCS16
EPCS64
The device implements the read silicon ID operation by driving the nCSsignal low
and then shifting in the read silicon ID operation code, followed by three dummy
bytes on the ASDIpin. The 8-bit silicon ID of the EPCS device is then shifted out on the
DATApin on the falling edge of the DCLKsignal. The device can terminate the read
silicon ID operation by driving the nCSsignal high after reading the silicon ID at least
one time. Sending additional clock cycles on DCLKwhile nCSis driven low can cause
the silicon ID to be shifted out repeatedly.
April 2014 Altera Corporation
Serial Configuration (EPCS) Devices Datasheet
INTEL [ INTEL ]
