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Timing Information
Figure 19 shows the timing waveform for the read operation of the EPCS device.
Figure 19. Read Operation Timing Diagram
nCS
t
CH
DCLK
t
t
CL
t
nCLK2D
ODIS
DATA
ASDI
Bit N
Bit N 1
Bit 0
Add_Bit 0
Table 17 lists the EPCS device timing parameters for the read operation.
Table 17. Read Operation Parameters
Symbol
Parameter
Min
Max
Unit
Read clock frequency (from the FPGA or
embedded processor) for the read bytes
operation
—
20
MHz
fRCLK
Fast read clock frequency (from the FPGA or
embedded processor) for the fast read bytes
operation
—
40
MHz
tCH
DCLKhigh time
11
11
—
—
—
—
8
ns
ns
ns
ns
tCL
DCLKlow time
tODIS
Output disable time after read
Clock falling edge to DATA
tnCLK2D
8
1
Existing batches of EPCS1 and EPCS4 devices manufactured on 0.15 µm process
geometry support the AS configuration up to 40 MHz. However, batches of EPCS1
and EPCS4 devices manufactured on 0.18 µm process geometry support the AS
configuration only up to 20 MHz. EPCS16, EPCS64, and EPCS128 devices are not
affected.
f
For more information about product traceability and transition date to differentiate
between 0.15 µm process geometry and 0.18 µm process geometry of the EPCS1 and
EPCS4 devices, refer to the PCN 0514: Manufacturing Changes on EPCS Family.
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
