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EPCS Device Memory Access
Figure 11 shows the instruction sequence of the read bytes operation.
Figure 11. Read Bytes Operation Timing Diagram
nCS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
DCLK
Operation Code
24-Bit Address (1)
23 22 21
MSB
3
2
1
0
ASDI
DATA Out 1
DATA Out 2
7
High Impedance
7
6
5
4
3
2
1
0
DATA
MSB (2)
Notes to Figure 11:
(1) Address bit A[23]is a don't-care bit in the EPCS64 device. Address bits A[23..21]are don't-care bits in the EPCS16 device. Address bits
A[23..19]are don't-care bits in the EPCS4 device. Address bits A[23..17]are don't-care bits in the EPCS1 device.
(2) For .rpd files, the read sequence shifts out the LSB of the data byte first.
Fast Read Operation
The fast read operation code is b’0000 1011and it lists the MSB first. You can select
the device by driving the nCSsignal low. The fast read instruction code is followed by
a 3-byte address (A23-A0) and a dummy byte with each bit being latched-in during the
rising edge of the DCLKsignal. Then, the memory contents at that address is shifted out
on DATAwith each bit being shifted out at a maximum frequency of 40 MHz during
the falling edge of the DCLKsignal.
The first addressed byte can be at any location. The address is automatically increased
to the next higher address after each byte of data is shifted out. Therefore, the whole
memory can be read with a single fast read instruction. When the highest address is
reached, the address counter rolls over to 000000h, allowing the read sequence to
continue indefinitely.
The fast read instruction is terminated by driving the nCSsignal high at any time
during data output. Any fast read instruction is rejected during the erase, program, or
write operations without affecting the operation that is in progress.
Serial Configuration (EPCS) Devices Datasheet
April 2014 Altera Corporation
INTEL [ INTEL ]
