1–20
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–28. Cyclone III Devices Mini-LVDS Transmitter Timing Specifications (1), (2) (Part 2 of 2)
C6
C7, I7
Typ
C8, A7
Typ
Symbol
Modes
Unit
Min
Typ
Max
Min
Max
Min
Max
Output jitter
(peak to
peak)
—
—
—
500
—
—
500
—
—
550
ps
ps
20 – 80%,
tRISE
—
500
—
—
500
—
—
500
—
C
LOAD = 5 pF
20 – 80%,
tFALL
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
C
LOAD = 5 pF
—
(3)
tLOCK
ms
Notes to Table 1–28:
(1) Applicable for true and emulated mini-LVDS transmitter.
(2) True mini-LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated mini-LVDS transmitter is supported
at the output pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
