1–18
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
High-Speed I/O Specifications
Table 1–26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27.
(1), (2)
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
C6
C7, I7
C8, A7
Min Typ Max
Symbol
Modes
Unit
Min Typ Max Min Typ
Max
155.5
155.5
155.5
155.5
155.5
311
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
180
180
180
180
180
360
360
360
360
360
360
360
55
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
155.5 MHz
fHSCLK
(input clock
frequency)
5
5
5
5
5
5
5
5
5
5
5
5
311
MHz
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
311
100
80
70
40
20
10
45
—
311 Mbps
311 Mbps
311 Mbps
311 Mbps
311 Mbps
311 Mbps
311
311
Device operation in
Mbps
311
311
311
tDUTY
55
55
%
TCCS
200
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
—
—
—
—
500
—
—
—
—
550
—
ps
ps
20 – 80%, CLOAD
5 pF
=
=
tRISE
tFALL
500
500
500
20 – 80%, CLOAD
5 pF
—
—
500
—
—
1
—
—
500
—
—
1
—
—
500
—
—
1
ps
(3)
tLOCK
—
ms
Notes to Table 1–26:
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output
pin of all I/O banks.
(3) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications (1) (Part 1 of 2)
C6
C7, I7
C8, A7
Symbol
Modes
Unit
Min
5
Typ
—
—
—
—
—
—
Max
85
Min
5
Typ
—
—
—
—
—
—
Max
85
Min
5
Typ
—
—
—
—
—
—
Max
85
×10
×8
×7
×4
×2
×1
MHz
MHz
MHz
MHz
MHz
MHz
5
85
5
85
5
85
fHSCLK (input
clock
frequency)
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
85
5
170
5
170
5
170
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
