1–22
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 2 of 2)
C6
C7, I7
Min
C8, A7
Min
Symbol
Modes
Unit
Min
—
Max
500
1
Max
500
1
Max
550
1
Output jitter
(peak to peak)
—
—
—
—
—
—
ps
(2)
tLOCK
—
ms
Notes to Table 1–30:
(1) Emulated LVDS transmitter is supported at the output pin of all I/O banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
(1)
Table 1–31. Cyclone III Devices LVDS Receiver Timing Specifications
C6
C7, I7
Min
C8, A7
Symbol
Modes
Unit
Min
5
Max
437.5
437.5
437.5
437.5
437.5
437.5
875
Max
370
370
370
370
370
402.5
740
740
740
740
740
402.5
400
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
400
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
5
5
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
5
5
5
5
5
fHSCLK (input
clock frequency)
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
—
100
80
70
40
20
10
—
100
80
70
40
20
10
—
875
875
HSIODR
SW
875
875
437.5
400
Input jitter
tolerance
—
—
—
—
500
1
—
—
500
1
—
—
550
1
ps
(2)
tLOCK
ms
Notes to Table 1–31:
(1) LVDS receiver is supported at all banks.
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
External Memory Interface Specifications
Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
f
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to Literature: External Memory Interfaces.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
