Chapter 1: Cyclone III Device Datasheet
1–23
Switching Characteristics
Table 1–32 lists the FPGA sampling window specifications for Cyclone III devices.
Table 1–32. Cyclone III Devices FPGA Sampling Window (SW) Requirement – Read Side (1)
Column I/Os Row I/Os
Wraparound Mode
Memory Standard
Setup
Hold
Setup
Hold
Setup
Hold
C6
C7
C8
I7
DDR2 SDRAM
580
585
785
550
535
735
690
700
805
640
650
755
850
870
905
800
820
855
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
705
675
900
650
620
845
770
795
910
715
740
855
985
970
930
915
1085
1030
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
785
800
720
740
990
930
915
870
855
1115
1185
1210
1055
1125
1150
1050
1065
1005
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
765
745
945
710
690
890
855
880
955
800
825
900
1040
1000
1130
985
945
1075
A7
DDR2 SDRAM
DDR SDRAM
805
880
745
820
1020
955
960
935
1145
1220
1250
1085
1160
1190
QDRII SRAM
1090
1030
1105
1045
Note to Table 1–32:
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Table 1–33 lists the transmitter channel-to-channel skew specifications for Cyclone III
devices.
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1)
(Part 1 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory
Standard
I/O Standard
Lead
Lag
C6
Lead
Lag
Lead
Lag
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
790
870
750
860
780
830
380
490
320
350
410
510
790
870
750
860
780
830
380
490
320
350
410
510
890
970
850
960
880
930
480
590
420
450
510
610
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
C7
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
INTEL [ INTEL ]
