1–24
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1)
(Part 2 of 2)
Column I/Os (ps)
Row I/Os (ps)
Wraparound Mode (ps)
Memory
I/O Standard
Standard
Lead
915
Lag
410
545
340
380
450
570
Lead
Lag
410
545
340
380
450
570
Lead
1015
1125
980
Lag
510
645
440
480
550
670
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
915
1025
880
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
1025
880
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1010
910
1010
910
1110
1010
1110
1010
1010
C8
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
I7
1040
1180
1010
1160
1040
1190
440
600
360
410
490
630
1140
1280
1110
1260
1140
1290
540
700
460
510
590
730
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
961
1076
924
431
572
357
399
473
599
A7
961
1076
924
431
572
357
399
473
599
1061
1176
1024
1161
1056
1161
531
672
457
499
573
699
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1061
956
1061
956
1061
1061
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
1092
1239
1061
1218
1092
1250
462
630
378
431
515
662
1092
1239
1061
1218
1092
1250
462
630
378
431
515
662
1192
1339
1161
1318
1192
1350
562
730
478
531
615
762
DDR2 SDRAM
(2)
DDR SDRAM
SSTL-2 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
QDRII SRAM
Notes to Table 1–33:
(1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column
and row I/Os.
(2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required.
Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices.
Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 1 of 2)
Parameter
Clock period jitter
Symbol
tJIT(per)
tJIT(cc)
Min
-125
-200
Max
125
200
Unit
ps
Cycle-to-cycle period jitter
ps
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
