Chapter 1: Cyclone III Device Datasheet
1–21
Switching Characteristics
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications (1)
C6
C7, I7
Min
C8, A7
Min
Symbol
Modes
Unit
Min
5
Max
420
420
420
420
420
420
840
840
840
840
840
420
55
Max
370
370
370
370
370
402.5
740
740
740
740
740
402.5
55
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
5
5
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
HSIODR
tDUTY
TCCS
200
200
200
ps
Output jitter
(peak to peak)
—
—
—
—
500
1
—
—
500
1
—
—
550
1
ps
(2)
tLOCK
ms
Notes to Table 1–29:
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 1 of 2)
C6
C7, I7
Min
C8, A7
Min
Symbol
Modes
Unit
Min
5
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
Max
320
320
320
320
320
402.5
640
640
640
640
640
402.5
55
Max
275
275
275
275
275
402.5
550
550
550
550
550
402.5
55
×10
×8
×7
×4
×2
×1
×10
×8
×7
×4
×2
×1
—
—
5
5
5
5
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
5
5
5
5
f
HSCLK (input
clock frequency)
5
5
5
5
5
5
5
5
5
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
100
80
70
40
20
10
45
—
HSIODR
tDUTY
TCCS
200
200
200
ps
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 2
INTEL [ INTEL ]
