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EP3C16Q240C8N 参数 Datasheet PDF下载

EP3C16Q240C8N图片预览
型号: EP3C16Q240C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 15408 CLBs, 472.5MHz, 15408-Cell, CMOS, PQFP240, 34.60 X 34.60 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LEAD FREE, QFP-240]
分类和应用: 时钟可编程逻辑
文件页数/大小: 34 页 / 836 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone III Device Datasheet  
1–17  
Switching Characteristics  
Table 1–24 lists the active configuration mode specifications for Cyclone III devices.  
Table 1–24. Cyclone III Devices Active Configuration Mode Specifications  
Programming Mode  
Active Parallel (AP)  
Active Serial (AS)  
DCLK Range  
20 – 40  
Unit  
MHz  
MHz  
20 – 40  
Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.  
(1)  
Table 1–25. Cyclone III Devices JTAG Timing Parameters  
Symbol  
tJCP  
Parameter  
Min  
40  
20  
20  
1
Max  
15  
15  
15  
25  
25  
25  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
TCK clock period  
tJCH  
TCK clock high time  
TCK clock low time  
tJCL  
tJPSU_TDI JTAG port setup time for TDI  
tJPSU_TMS JTAG port setup time for TMS  
3
tJPH  
JTAG port hold time  
10  
5
tJPCO  
tJPZX  
tJPXZ  
tJSSU  
tJSH  
JTAG port clock to output (2)  
JTAG port high impedance to valid output (2)  
JTAG port valid output to high impedance (2)  
Capture register setup time  
Capture register hold time  
10  
tJSCO  
tJSZX  
tJSXZ  
Update register clock to output  
Update register high impedance to valid output  
Update register valid output to high impedance  
Notes to Table 1–25:  
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27.  
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS  
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.  
Periphery Performance  
This section describes periphery performance, including high-speed I/O, external  
memory interface, and IOE programmable delay.  
I/O performance supports several system interfacing, for example, the high-speed  
I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using  
the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM  
interfacing speeds with typical DDR SDRAM memory interface setup. I/O using  
general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are  
capable of a typical 200 MHz interfacing frequency with a 10 pF load.  
1
Actual achievable frequency depends on design- and system-specific factors. Perform  
HSPICE/IBIS simulations based on your specific design and system setup to  
determine the maximum achievable frequency in your system.  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 2  
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