1–16
Chapter 1: Cyclone III Device Datasheet
Switching Characteristics
Table 1–20. Cyclone III Devices PLL Specifications (1)
Symbol
(Part 2 of 2)
Parameter
Min
Typ
Max
Unit
fSCANCLK
scanclk frequency
—
—
100
MHz
Notes to Table 1–20:
(1) VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
jitter of the PLL, when an input jitter of 30 ps is applied.
(6) With 100 MHz scanclk frequency.
Embedded Multiplier Specifications
Table 1–21 describes the embedded multiplier specifications for Cyclone III devices.
Table 1–21. Cyclone III Devices Embedded Multiplier Specifications
Resources Used
Performance
C7, I7, A7
Mode
9 × 9-bit
Unit
Number of Multipliers
C6
C8
1
1
340
300
250
260
MHz
MHz
multiplier
18 × 18-bit
multiplier
287
200
Memory Block Specifications
Table 1–22 describes the M9K memory block specifications for Cyclone III devices.
Table 1–22. Cyclone III Devices Memory Block Performance Specifications
Resources Used
Performance
Memory
Mode
M9K
LEs
C6
C7, I7, A7
C8
Unit
Memory
FIFO 256 × 36
47
0
1
1
1
1
315
315
315
315
274
274
274
274
238
238
238
238
MHz
MHz
MHz
MHz
Single-port 256 × 36
M9K Block
Simple dual-port 256 × 36 CLK
True dual port 512 × 18 single CLK
0
0
Configuration and JTAG Specifications
Table 1–23 lists the configuration mode specifications for Cyclone III devices.
Table 1–23. Cyclone III Devices Configuration Mode Specifications
Programming Mode
Passive Serial (PS)
DCLK Fmax
133
Unit
MHz
MHz
(1)
Fast Passive Parallel (FPP)
100
Note to Table 1–23:
(1) EP3C40 and smaller density members support 133 MHz.
Cyclone III Device Handbook
Volume 2
July 2012 Altera Corporation
INTEL [ INTEL ]
