Register Description
Bits
Type
Reset
Description
9
RW
0
Secondary Discard Timer (SDT): Sets the maximum number of PCI clock
cycles that the Intel® 6700PXH 64-bit PCI Hub waits for an initiator on the PCI
bus to repeat a delayed transaction request. The counter starts once the
delayed transaction completion is at the head of the queue. If the master has
not repeated the transaction at least once before the counter expires, the
Intel® 6700PXH 64-bit PCI Hub discards the transaction from its queues.
0 = The PCI master timeout value is between 215 and 216 PCI clocks.
1 = The PCI master timeout value is between 210 and 211 PCI clocks.
8
7
RW
RO
0
0
Primary Discard Timer (PDT): Not relevant to the PCI Express* interface.
This bit is RW for software compatibility only.
Fast Back-to-Back Enable (FBE): The Intel® 6700PXH 64-bit PCI Hub
cannot generate fast back-to-back cycles on the PCI bus from PCI Express*
interface initiated transactions.
6
RW
0
Secondary Bus Reset (SBR): Controls PxPCIRST# assertion on the PCI bus.
0 = Intel® 6700PXH 64-bit PCI Hub deasserts PxPCIRST#.
1 = Intel® 6700PXH 64-bit PCI Hub asserts PxPCIRST#. When PxPCIRST#
is asserted, the data buffers between the PCI Express* interface and PCI and
the PCI bus interface logic are initialized back to reset conditions. The PCI
Express* interface logic and the Intel® 6700PXH 64-bit PCI Hub configuration
registers are not affected. SHPC interface logic, SHPC working space
registers, I/OxAPIC interface logic and I/OxAPIC registers are not reset on this
bit being set.
Note that once this bit is set, the Intel® 6700PXH 64-bit PCI Hub will complete
the currently running transaction on the PCI bus and then reset the bus. It is
the responsibility of software to make sure that all pending transactions with
the bus segment are complete before setting this bit.
5
RW
0
Master Abort Mode (MAM): Controls the Intel® 6700PXH 64-bit PCI Hub's
behavior when a master abort occurs on either interface.
Master Abort on the PCI Express* interface (Memory reads only):
0 = The Intel® 6700PXH 64-bit PCI Hub asserts PxTRDY# on the PCI/PCI-X
bus. It drives all '1's for reads.
1 = The Intel® 6700PXH 64-bit PCI Hub returns a target abort on the
PCI/PCI-X bus.
Master Abort PCI (Completion required packets only):
0 = Normal completion status will be returned on the PCI Express* interface.
1 = Target abort completion status will be returned on the PCI Express*
interface.
4
RW
0
VGA 16-bit Decode (V16D): This bit enables the bridge to provide 16-bit
decoding of the VGA I/O address precluding the decode of VGA alias
addresses every 1 KB. This bit requires the VGA enable bit (bit 3 of this
register) to be set to 1.
0 = Disable
1 = Enable
Intel® 6700PXH 64-bit PCI Hub Datasheet
97
INTEL [ INTEL ]
