Register Description
3.5.1.18
3.5.1.19
3.5.1.20
Offset 20h: MB—Memory Base Register (D0:F0, F2)
Offset:
Default Value: 0000h
20–21h
Attribute: RW, RO
Size: 16 bits
This register defines the base (aligned to a 1-Mbyte boundary) of the prefetchable memory area of
the bridge. Accesses from the PCI Express* interface that are within the range specified in this
register will be sent to PCI if the memory space enable bit is set.
Accesses from PCI that are outside the range specified will be forwarded to the PCI Express*
interface if the bus master enable bit is set.
Bits
Type
Reset
Description
15:4
RW
0
Memory Base (MB): These bits are compared with bits [31:20] of the
incoming address to determine the lower 1 MB aligned value (inclusive) of the
range. The incoming address must be greater than or equal to this value.
3:0
RO
0
Reserved.
Offset 22h: ML—Memory Limit Register (D0:F0, F2)
Offset:
Default Value: 0000h
22–23h
Attribute: RW, RO
Size: 16 bits
This register defines the limit (aligned to a 1MByte boundary) of the prefetchable memory area of
the bridge. Accesses from the PCI Express* interface that are within the range specified in this
register will be sent to PCI if the memory space enable bit is set.
Accesses from PCI that are outside the range specified will be forwarded to the PCI Express*
interface if the bus master enable bit is set.
Bits
Type
Reset Description
15:4
RW
0
Memory Limit (ML): These bits are compared with bits [31:20] of the incoming
address to determine the upper 1MByte aligned value (exclusive) of the range.
The incoming address must be less than this value.
3:0
RO
0
Reserved.
Offset 24h: PMB—Prefetchable Memory Base Register
(D0:F0, F2)
Offset:
Default Value: 0001h
24–25h
Attribute: RW, RO
Size: 16 bits
Defines the base (aligned to a 1MByte boundary) of the prefetchable memory area of the bridge.
Accesses from the PCI Express* interface that are within the ranges specified in this register will
be sent to PCI if the memory space enable bit is set.
Accesses from PCI that are outside the ranges specified will be forwarded to the PCI Express*
interface if the bus master enable bit is set.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
