Register Description
Bits
Type
Reset
Description
7
RW
0
Peer Memory Read Enable (PMRE):
0 = Normal operation. Peer memory reads are not allowed and all memory
reads from the PCI bridge will be sent to PCI Express* regardless of the
address.
1 = Normal + Peer-to-Peer mode of operation. Intel® 6700PXH 64-bit PCI Hub
supports full Peer-to-Peer read/write but it’s not performance optimized.
6
5
RO
0
0
Reserved.
RW
SHPC GPE Message Enable (SGME): Enable Redirection of hot plug
interrupts to Assert/Deassert_GPE Messages on the PCI Express* bus.
4:0
RO
0
Reserved.
3.5.1.31
Offset 42h: MTT—Multi-Transaction Timer Register (D0:F0, F2)
Offset:
Default Value: 00h
42h
Attribute: RW, RO
Size: 8 bits
This register controls the amount of time that the Intel® 6700PXH 64-bit PCI Hub's arbiter allows
a PCI initiator to perform multiple back-to-back transactions on the PCI bus. The number of clocks
programmed in the Multi-Transition Timer represents the guaranteed time slice (measured in PCI
clocks) allotted to the current agent, after which the arbiter will grant another agent that is
requesting the bus.
Bits
Type
Reset
Description
7:3
RW
0
Timer Count Value (MTC): This field specifies the amount of time that grant
remains asserted to a master continuously asserting its request for multiple
transfers. This field specifies the count in an 8-clock (PCI clock) granularity.
2:0
RO
0
Reserved.
3.5.1.32
Offset 43h: PCLKC—PCI Clock Control Register (D0:F0, F2)
Offset:
Default Value: FFh
43h
Attribute: RW, RO
Size: 8 bits
This register controls the enable or disable of the Intel® 6700PXH 64-bit PCI Hub PCI clock
outputs PxPCLKO[6:0].
Bits
Type
Reset
Description
7
RO
1
Reserved.
6:0
RW
1111111b PCI Clock Control (PCLKC): These bits enable the PCI clock output buffers,
when 1. Otherwise the buffers are tri-stated. Bit 6 corresponds to
PxPCLKO[6], bit 5 corresponds to PxPCLKO[5], etc.
100
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
