Register Description
Note that even though this register specifies a valid prefetchable memory window, the Intel®
6700PXH 64-bit PCI Hub never prefetches through this window in the outbound direction (reads
from PCI Express* to PCI). In the inbound direction, prefetchability through this window is
controlled through the Intel® 6700PXH 64-bit PCI Hub configuration register bits 4:3, at offset
40h.
Bits
Type
Reset Description
15:4
RW
0
Prefetchable Memory Base (PMB): These bits are compared with bits [31:20]
of the incoming address to determine the lower 1 MB aligned value (inclusive)
of the range. The incoming address must be greater than or equal to this value.
3:0
RO
1
64-bit Indicator (IS64B): Indicates that 64-bit addressing is supported for the
limit. This value must be in agreement with the IS64L field.
3.5.1.21
Offset 26h: PML—Prefetchable Memory Limit Register
(D0:F0, F2)
Offset:
Default Value: 0001h
26–27h
Attribute: RW, RO
Size: 16 bits
Defines the limit (aligned to a 1MByte boundary) of the prefetchable memory area of the bridge.
Accesses from the PCI Express* interface that are within the ranges specified in this register will
be sent to PCI if the memory space enable bit is set.
Accesses from PCI that are outside the ranges specified will be forwarded to the PCI Express*
interface if the bus master enable bit is set.
Note that even though this register specifies a valid prefetchable memory window, the Intel®
6700PXH 64-bit PCI Hub never prefetches through this window in the outbound direction (reads
from PCI Express* to PCI). In the inbound direction, prefetchability through this window is
controlled through the Intel® 6700PXH 64-bit PCI Hub configuration register bits 4:3, at offset
40h.
Bits
Type
Reset
Description
15:4
RW
0
Prefetchable Memory Limit (PML): These bits are compared with bits
[31:20] of the incoming address to determine the upper 1MByte aligned value
(exclusive) of the range. The incoming address must be less than this value.
3:0
RO
1
64-bit Indicator (IS64L): Indicates that 64-bit addressing is supported for the
limit. This value must be in agreement with the IS64B field.
3.5.1.22
Offset 28h: PMB_UPPER—Prefetchable Base Upper
32 Bits Register (D0:F0, F2)
Offset:
Default Value: 00000000h
28–2Bh
Attribute: RW, RO
Size: 32 bits
This defines the upper 32 bits of the prefetchable address base register.
Bits
Type
Reset
Description
31:0
RW
0
Prefetchable Memory Base Upper Portion (PMBU): All bits are
read/writeable; the Intel® 6700PXH 64-bit PCI Hub supports full 64-bit
addressing.
94
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
