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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Register Description  
3.5.1.27  
Offset 3Ch: INTRL—Interrupt Line Register (D0:F0, F2)  
Offset:  
Default Value: 00h  
3Ch  
Attribute:RW  
Size: 8 bits  
This register communicates interrupt line routing information.  
Bits  
Type  
Reset  
Description  
7:0  
RW  
0
Interrupt Line (INTRL): This register is used to convey the interrupt line  
routing information between the initialization code and the device driver. This  
is not used by the Intel® 6700PXH 64-bit PCI Hub.  
3.5.1.28  
Offset 3Dh: INTRP—Interrupt Pin Register (D0:F0, F2)  
Offset:  
3Dh  
Attribute:RW  
Size: 8 bits  
Default Value: 01h (Function 0)  
02h (Function 2)  
This register is used to indicate which interrupt virtual wires, if any, the Intel® 6700PXH 64-bit  
PCI Hub uses on behalf of internal sources.  
Bits  
Type  
Reset  
Description  
7:0  
RO  
Function 0: 01h  
Function 2: 02h  
Interrupt Pin (INTR): The Intel® 6700PXH 64-bit PCI Hub has an  
integrated standard hot plug controller, which is a source of  
interrupts. The logical primary bus interrupt pin is INTA# for Function  
0, with a corresponding register value of 01h. The interrupt pin is  
INTB# for Function 2, with a corresponding register value of 02h.  
Note that the hot plug interrupt is routed internally to IRQ#[23] of the  
corresponding I/OxAPIC.  
3.5.1.29  
Offset 3Eh: BRIDGE_CNT—Bridge Control Register  
(D0:F0, F2)  
Offset:  
Default Value: 0000h  
3E–3Fh  
Attribute: RW, RWC; RO  
Size: 16 bits  
This register provides extensions to the Command register that are specific to a bridge. The Bridge  
Control register provides many of the same controls for the secondary interface that are provided  
by the Command register for the primary interface. Some bits affect operation of both interfaces of  
the bridge.  
Bits  
Type  
Reset  
Description  
15:12  
11  
RO  
0
0
Reserved.  
RW  
Discard Timer SERR Enable (DTSE): Controls the generation of ERR_UNC  
on the primary interface in response to a timer discard on the secondary  
interface.  
0 = Do not generate ERR_UNC on a secondary timer discard  
1 = Generate ERR_UNC in response to a secondary timer discard  
10  
RWC  
0
Discard Timer Status (DTS): Software clears this bit by writing a 1 to it.  
1 = Secondary discard timer expires (there is no discard timer for the primary  
interface)  
96  
Intel® 6700PXH 64-bit PCI Hub Datasheet