Register Description
3.5.1.33
3.5.1.34
3.5.1.35
Offset 44h: EXP_CAPID—PCI Express* Capability
Identifier Register (D0:F0, F2)
Offset:
Default Value: 10h
44h
Attribute: RO
Size: 8 bits
Bits
Type
Reset
Description
7:0
RO
10h
PCI Express* Capability Identifier (PCIECAPI): Indicates PCI Express*
capability.
Offset 45h: EXP_NXTP—PCI Express* Next Pointer Register
(D0:F0, F2)
Offset:
Default Value: 5Ch
45h
Attribute: RO
Size: 8 bits
Bits
Type
Reset
Description
7:0
RO
5Ch
Next Pointer (MNPTR): Points to the next capabilities list pointer, which is the
MSI capability.
Offset 46h: EXP_CAP—PCI Express* Capability Register
(D0:F0, F2)
Offset:
Default Value: 0030h
46 - 47h
Attribute: RO
Size: 16 bits
Bits
Type
Reset
Description
15:8
7:4
RO
RO
0
Reserved.
7h
Device/Port Type(DEVPORT): Indicates the type of PCI Express* logical
device. Value of 7h indicates that this is a PCI/PCI-X to PCI Express* Bridge.
3:0
RO
1h
Capability Version (CAPVER): Indicates PCI-SIG defined PCI Express*
capability structure version number. Must be 1h for this version.
3.5.1.36
Offset 48h: EXP_DEVCAP—PCI Express* Device Capabilities
Register (D0:F0, F2)
Offset:
Default Value: 00000001h
48 – 4Bh
Attribute: RO
Size: 32 bits
This register contains information about the PCI Express* link capabilities.
Bits
Type
Reset
Description
31:12
11:9
RO
RO
0
0
Reserved.
Endpoint L1 Acceptable Latency (L1AL): The Intel® 6700PXH 64-bit PCI
Hub does not support L1 Link State Power Management (LSPM).
8:6
RO
0
Endpoint L0s Acceptable Latency (L0AL): The Intel® 6700PXH 64-bit PCI
Hub wants the least possible latency out of L0s.
Intel® 6700PXH 64-bit PCI Hub Datasheet
101
INTEL [ INTEL ]
