Register Description
3.5.1.23
Offset 2Ch: PML_UPPER—Prefetchable Limit Upper
32 Bits Register (D0:F0, F2)
Offset:
Default Value: 00000000h
2C–2Fh
Attribute: RW
Size: 32 bits
This defines the upper 32 bits of the prefetchable address limit register.
Bits
Type
Reset
Description
31:0
RW
0
Prefetchable Memory Limit Upper Portion (PMLU): All bits are
read/writeable; the Intel® 6700PXH 64-bit PCI Hub supports full 64-bit
addressing.
3.5.1.24
3.5.1.25
3.5.1.26
Offset 30h: IOLU16—I/O Limit Upper 16 Bits Register
(D0:F0, F2)
Offset:
Default Value: 0000h
30–31h
Attribute: RO
Size: 16 bits
Since I/O is limited to 64 Kbytes, this register is reserved and not used.
Bits
Type
Reset
Description
15:0
RO
0
I/O Limit High 16 Bits (IOLH): Reserved.
Offset 32h: IOBU16—I/O Base Upper 16 Bits Register
(D0:F0, F2)
Offset:
Default Value: 0000h
32–33h
Attribute: RO
Size: 16 bits
Since I/O is limited to 64 Kbytes, this register is reserved and not used.
Bits
Type
Reset
Description
15:0
RO
0
I/O Base High 16 Bits (IOBH): Reserved.
Offset 34h: CAPP—Capabilities Pointer Register
(D0:F0, F2)
Offset:
Default Value: 44h
34h
Attribute: RO
Size: 8 bits
This register is used to point to a linked list of additional capabilities implemented by the Intel®
6700PXH 64-bit PCI Hub.
Bits
Type
Reset
Description
7:0
RO
44h
Capabilities Pointer (PTR): This field indicates that the pointer for the first
entry in the PCI Express* Capability List is at offset 44h in configuration
space.
Intel® 6700PXH 64-bit PCI Hub Datasheet
95
INTEL [ INTEL ]
