Register Description
Bits
Type
Reset
Description
3
RW
0
VGA Enable (VGAE): Modifies the Intel® 6700PXH 64-bit PCI Hub's
response to VGA compatible address.
1 = Intel® 6700PXH 64-bit PCI Hub forwards the following transactions from
the PCI Express* interface to PCI regardless of the value of the I/O base and
I/O limit registers. The transactions are qualified by the memory enable and
I/O enable in the command register.
Memory addresses: 000A0000h–000BFFFFh
I/O addresses: 3B0h–3BBh and 3C0h-3DFh. For the I/O addresses, bits
[63:16] of the address must be ‘0’, and bits [15:10] of the address are ignored
(i.e., aliased).
0 = The same holds true from secondary accesses to the primary interface in
reverse. That is, when the bit is 0, memory and I/O addresses on the
secondary interface between the above ranges will be forwarded to the PCI
Express* interface.
2
1
0
RW
RW
RW
0
0
0
ISA Enable (IE): Modifies the response by the bridge to ISA I/O addresses.
This only applies to I/O addresses that are enabled by the I/O Base and I/O
Limit registers and are in the first 64 KB of PCI I/O space.
0 = Disable.
1 = Enable. The bridge will block any forwarding from primary to secondary of
I/O transactions addressing the last 768 bytes in each 1 KB block (offsets
100h to 3FFh). This bit has no effect on transfers originating on the secondary
bus as the Intel® 6700PXH 64-bit PCI Hub does not forward I/O transactions
across the bridge.
SERR Enable (SE): Controls the forwarding of secondary interface SERR#
assertions on the primary interface.
0 = Disable.
1 = Enable. The Intel® 6700PXH 64-bit PCI Hub will send a PCI Express*
interface SERR cycle when all of the following are true:
SERR# is asserted on the secondary interface
This bit is set
The SERR Enable bit in the Command Register is set
Parity Error Response Enable (PERE): Controls the Intel® 6700PXH 64-bit
PCI Hub's response to address and data parity errors on the secondary
interface.
0 = The bridge must ignore any parity errors that it detects and continue
normal operation. The Intel® 6700PXH 64-bit PCI Hub must generate parity
even if parity error reporting is disabled.
1 = Intel® 6700PXH 64-bit PCI Hub will report parity errors.
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Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
