Register Description
Bits
Type
Reset
Description
13
12
11
RWC
0
Received Master Abort (RMA):
This bit reports the detection of a Master-Abort termination when the Intel®
6700PXH 64-bit PCI Hub is acting as a PCI/PCI-X master or when the Intel®
6700PXH 64-bit PCI Hub receives a PCI-X Split Completion Message
indicating Master Abort.
0 = Master-Abort not detected on the PCI/PCI-X interface.
1 = Master-Abort detected on the PCI/PCI-X interface
Software clears this bit by writing a 1 to it.
RWC
0
Received Target Abort (RTA):
This bit reports the detection of a Target-Abort termination when the Intel®
6700PXH 64-bit PCI Hub is acting as a PCI/PCI-X master or when the Intel®
6700PXH 64-bit PCI Hub signals a PCI-X Split Completion Message indicating
Target Abort.
0 = Target-Abort not detected on the PCI/PCI-X interface.
1 = Target-Abort detected on the PCI/PCI-X interface
Software clears this bit by writing a 1 to it.
RWC
0
Signaled Target Abort (STA):
This bit reports the signaling of a Target-Abort termination by the Intel®
6700PXH 64-bit PCI Hub when it responds as the target of a transaction on
the PCI/PCI-X interface or when the Intel® 6700PXH 64-bit PCI Hub signals a
PCI-X Split Completion Message with Target Abort.
0 = Target-Abort not signaled on the PCI/PCI-X interface.
1 = Target-Abort signaled on the PCI/PCI-X interface.
Software clears this bit by writing a 1 to it.
10:9
8
RO
01b
0
DEVSEL# Timing (DVT): This field indicates that the Intel® 6700PXH 64-bit
PCI Hub responds in medium decode time to all cycles targeting the PCI
Express* interface.
RWC
Master Data Parity Error (MDP): This bit is used to report the detection of an
uncorrectable data error. This Bit is set if the Intel® 6700PXH 64-bit PCI Hub
is the bus master of the transaction on the PCI/PCI-X interface, the Parity
Error Response bit in the Bridge Control register is set, and either of the
following two conditions occur:
•
•
The Intel® 6700PXH 64-bit PCI Hub asserts PERR# on a read transaction
The Intel® 6700PXH 64-bit PCI Hub detects PERR# asserted on a write
transaction
In addition, when in PCI-X mode, this bit is set if either of the following occur:
•
The Intel® 6700PXH 64-bit PCI Hub detects an uncorrectable data error
in a Split Completion or Split Completion Message.
•
The Intel® 6700PXH 64-bit PCI Hub receives a Split Completion Message
for a non-posted write indicating an Uncorrectable (Split) Write Data Error.
0 = No uncorrectable data error detected on the PCI/PCI-X interface.
1 = Uncorrectable data error detected on the PCI/PCI-X interface.
Once set, this bit remains set until it is reset by writing a 1 to this bit location. If
the Parity Error Response bit is cleared, this bit is never set.
7
RO
1
Fast Back-to-Back Transactions Capable (FBTC): Indicates that the
secondary interface of the Intel® 6700PXH 64-bit PCI Hub can receive fast
back-to-back cycles.
6
5
RO
RO
0
1
Reserved.
66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66
MHz capable.
4:0
RO
0
Reserved.
92
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
