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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Register Description  
3.5.1.16  
Offset 1Dh: IOL—I/O Limit Register (D0:F0, F2)  
Offset:  
Default Value: 00h  
1Dh  
Attribute: RW, RO  
Size: 8 bits  
This register defines the limit (aligned to a 4-Kbyte boundary) of the I/O area of the bridge.  
Accesses from the PCI Express* interface that are within the ranges specified in this register will  
be sent to PCI if the I/O space enable bit is set. Accesses from PCI that are outside the ranges  
specified will master abort.  
Bits  
Type  
Reset  
Description  
7:4  
RW  
0
I/O Limit Address Bits [15:12] (IOLA): Defines the top address of an  
address range to determine when to forward I/O transactions from PCI  
Express* to PCI. These bits correspond to address lines 15:12 for 4 KB  
alignment. Bits [11:0] are assumed to be FFFh.  
3:2  
1:0  
RW  
RO  
0
0
I/O Limit Address Bits [11:10] (IOLA1K): When the EN1K bit is set in the  
Intel® 6700PXH 64-bit PCI Hub Configuration register (CNF), these bits  
become read/write and are compared with I/O address bits [11:10] to  
determine the 1 KB limit address. When the EN1K bit is cleared, this field  
becomes Read Only.  
RO  
I/O Limit Addressing Capability (IOLC): These bits are hardwired to ‘0’,  
indicating support for only 16-bit I/O addressing.  
3.5.1.17  
Offset 1Eh: SECSTS—Secondary Status Register  
(D0:F0, F2)  
Offset:  
Default Value: 02A0h  
1E–1Fh  
Attribute: RWC, RO  
Size: 16 bits  
Bits  
Type  
Reset  
Description  
15  
RWC  
0
Detected Parity Error (DPE):  
This bit reports the detection of an uncorrectable address, attribute or data  
error by the Intel® 6700PXH 64-bit PCI Hub’s PCI/PCI-X interface. This bit is  
set when any one of the following three conditions are true:  
The Intel® 6700PXH 64-bit PCI Hub detects an uncorrectable address or  
attribute error as a potential target.  
The Intel® 6700PXH 64-bit PCI Hub detects an uncorrectable data error  
when the target of a write transaction or a PCI-X Split Completion.  
The Intel® 6700PXH 64-bit PCI Hub detects an uncorrectable data error  
when the master of a read transaction (immediate read data or PCI-X Split  
Response)  
This bit gets set even if the Parity Error Response Enable bit (bit 0 of offset  
3E–3Fh) of the Bridge Control Register.  
0 = Uncorrectable address, attribute or data error not detected on the  
PCI/PCI-X interface.  
1 = Uncorrectable address, attribute or data error detected on the PCI/PCI-X  
interface.  
Software clears this bit by writing a 1 to it.  
14  
RWC  
0
Received System Error (RSE):  
This bit reports the detection of a SERR# assertion on the PCI/PCI-X  
interface.  
0 = SERR# assertion on the PCI/PCI-X interface has not been detected.  
1 = SERR# assertion on the PCI/PCI-X interface has been detected.  
Software clears this bit by writing a 1 to it.  
Intel® 6700PXH 64-bit PCI Hub Datasheet  
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