Register Description
3.5.1.14
Offset 1Bh: SLT—Secondary Latency Timer (D0:F0, F2)
Offset:
Default Value: 00h (PCI)
40h (PCI-X)
1Bh
Attribute: RW, RO
Size: 8 bits
This timer controls the amount of time that the Intel® 6700PXH 64-bit PCI Hub will continue to
burst data on its secondary interface. The counter starts counting down from the assertion of
PxFRAME#. If the grant is removed, the expiration of this counter will result in the de-assertion of
PxFRAME#. If the grant has not been removed, then the Intel® 6700PXH 64-bit PCI Hub may
continue ownership of the bus. Secondary latency timer's default value should be 64 in PCI-X
mode (Refer to Section 1.12.2 of the PCI-X Protocol Addendum to the PCI Local Bus
Specification, Revision 2.0a, Rule 11).
Bits
Type
Reset
Description
7:3
RW
PCI – 00h
Secondary Latency Timer (SLT): This 5-bit value indicates the number
PCI-X – 40h of PCI clocks, in 8-clock increments, that the Intel® 6700PXH 64-bit PCI
Hub remains as a master of the PCI bus if another master is requesting
use of the PCI bus. Bit 6 defaults to 1 on reset when in PCI-X mode.
2:0
RO
0
Reserved.
3.5.1.15
Offset 1Ch: IOB—I/O Base Register (D0:F0, F2)
Offset:
Default Value: 00h
1Ch
Attribute: RW, RO
Size: 8 bits
This register defines the base and limit (aligned to a 4-Kbyte boundary) of the I/O area of the
bridge. Accesses from the PCI Express* interface that are within the ranges specified in this
register will be sent to PCI if the I/O space enable bit is set. Accesses from PCI that are outside the
ranges specified will master abort.
Bits
Type
Reset
Description
7:4
RW
0
I/O Base Address Bits [15:12] (IOBA): This field defines the bottom address
of an address range to determine when to forward I/O transactions from one
interface to the other. These bits correspond to address lines 15:12 for 4 KB
alignment. Bits 11:0 are assumed to be 000h.
3:2
1:0
RW
RO
0
0
I/O Base Address Bits [11:10] (IOBA1K): When the EN1K bit is set in the
Intel® 6700PXH 64-bit PCI Hub Configuration register (CNF), these bits
become read/write and are compared with I/O address bits [11:10] to
determine the 1 KB base address. When the EN1K bit is cleared, this field
becomes Read Only.
RO
I/O Base Addressing Capability (IOBC): These are hardwired to ‘0’,
indicating support for only 16-bit I/O addressing.
90
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
