Register Description
3.5.1.8
Offset 0Dh: MLT—Master Latency Timer Register (D0:F0, F2)
Offset:
Default Value: 00h
0Dh
Attribute: RW
Size: 8 bits
This register does not apply to the PCI Express* interface and is maintained as RW for software
compatibility.
Bits
Type
Reset
Description
7:3
2:0
RW
RO
0
0
Time Value (TV): RW used for software compatibility only.
Reserved.
3.5.1.9
Offset 0Eh: HEADTYP—Header Type Register (D0:F0, F2)
Offset:
Default Value: 81h
0Eh
Attribute: RO
Size: 8 bits
This register is used to indicate the layout for bytes 10h through 3Fh of the device’s configuration
space.
Bits
Type
Reset
Description
7
RO
1
Multi-Function Device (MFD): Reserved as ‘1’ to indicate the bridge is a
multi-function device.
6:0
RO
01h
Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in
configuration space. Reads as 01h to indicate that the register layout
conforms to the standard PCI Express*-to-PCI/PCI-X bridge layout.
3.5.1.10
Offset 10h: SHPC_BAR—SHPC 64-bit Base Address Register
(D0:F0, F2)
Offset:
Default Value: 00000008h
10-17h
Attribute: RW, RO
Size: 64 bits
This register is used to access the SHPC working register set.
Note: When hot plug is disabled (HPx_SLOT[3] = 0), this register is RESERVED and set to 0h.
Bits
Type
Reset
Description
63:12
RW
0
Base Address (BA): These bits are used by BIOS to understand that SHPC
needs 4 Kbytes of memory space and then write a valid 4Kbyte aligned base
address.
11:4
3
RO
RO
0
0
Reserved.
Prefetchable (PF_SHPC): This bit is a read-only 0 to indicate that this
register needs to be mapped into the non-prefetchable space.
2:1
0
RO
RO
10b
0
Type (TYP_SHPC): These bits are read-only with a reset default of 10b,
indicating that this register can map anywhere in the 64-bit memory space.
Memory Space Indicator (MEMSI): This bit is a read-only 0 indicating that
this Base Address Register maps into memory space.
88
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
