Register Description
Bits
Type
Reset
Description
3
RO
0
Interrupt Status (INTSTS): This bit reflects the state of the SHPC interrupt,
when the interrupt is generated via the IRQ[23]# wire (not via MSI). Only
when the INTx mask bit in the command register is a 0 and this Interrupt
Status bit is a 1, and MSI is disabled will the SHPC assert the IRQ[23]# signal
to the I/OxAPIC. Setting the INTx mask bit to a 1 has no effect on the setting
of this bit.
2:0
RO
0
Reserved.
3.5.1.5
Offset 08h: REVID—Revision ID Register (D0:F0, F2)
Offset:
Default Value: 00h
08h
Attribute: RO
Size: 8 bits
Bits
Type
Reset
Description
7:0
RO
0
Revision ID (REVID): This indicates the stepping of the Intel® 6700PXH
64-bit PCI Hub:
00h = A0 stepping.
04h = B0 stepping.
08h = C0 stepping.
3.5.1.6
Offset 09h: CC—Class Code Register (D0:F0, F2)
Offset:
Default Value: 060400h
09–0Bh
Attribute: RO
Size: 24 bits
This contains the class code, sub class code, and programming interface for the device.
Bits
Type
Reset
Description
23:16
RO
06h
Base Class Code (BCC): The value of "06h" indicates that this is a bridge
device.
15:8
7:0
RO
RO
04h
0
Sub Class Code (SCC): 8-bit value that indicates this is of type PCI-to-PCI
bridge.
Programming Interface (PIF): Indicates that this is standard (non-
subtractive) PCI-to-PCI bridge.
3.5.1.7
Offset 0Ch: CLS—Cache Line Size Register (D0:F0, F2)
Offset:
Default Value: 00h
0Ch
Attribute: RW
Size: 8 bits
This indicates the cache line size of the system.
Bits
Type
Reset
Description
7:0
RW
0
Cache Line Size (CLS): This field is implemented by PCI Express* devices as
a RW field for legacy compatibility purposes but has no impact on any PCI
Express* device functionality.
Intel® 6700PXH 64-bit PCI Hub Datasheet
87
INTEL [ INTEL ]
