Register Description
3.5.1.4
Offset 06h: STS—Status Register (D0:F0, F2)
Offset:
Default Value: 0010h
06–07h
Attribute: RWC, RO
Size: 16 bits
Bits
Type
Reset
Description
15
RWC
0
Detected Parity Error (DPE):
0 = Software clears this bit by writing a 1 to it.
1 = Intel® 6700PXH 64-bit PCI Hub detected a data parity error on the PCI
Express* bus interface or peer PCI segment. This bit gets set even if the
Parity Error Response (bit 6 of the command register) is not set. Indicates
that a parity error was detected on cycles targeting the I/OxAPIC.
14
13
12
11
RWC
RWC
RWC
RWC
0
0
0
0
Signaled System Error (SSE): This bit is used for PCI-compatible error
signaling on the PCI Express* bus.
0 = Software clears this bit by writing a 1 to it.
1 = SERR# is reported to the PCI Express* interface.
Received Master-Abort (RMA):
0 = Software clears this bit by writing a 1 to it.
1 = Intel® 6700PXH 64-bit PCI Hub is acting as master on the PCI Express*
interface and receives a completion packet with master abort status.
Received Target-Abort (RTA):
0 = Software clears this bit by writing a 1 to it.
1 = Intel® 6700PXH 64-bit PCI Hub is acting as master on the PCI Express*
interface and receives a completion packet with target abort status.
1 = Signaled Target Abort (STA):
This bit reports the signaling of a Target-Abort termination by the Intel®
6700PXH 64-bit PCI Hub when it responds as the target of a transaction on
the PCI/PCI-X interface or when the Intel® 6700PXH 64-bit PCI Hub signals a
PCI-X Split Completion Message with Target Abort.
0 = Target Abort not signaled on the PCI/PCI-X interface.
1 = Target Abort signaled on the PCI/PCI-X interface.
Software clears this bit by writing a 1 to it.
10:9
8
RO
0
0
DEVSEL# Timing (DVT): These bits have no meaning on the PCI Express*
interface. Hardwired to 0.
RWC
Master Data Parity Error (MDP):
0 = Software clears this bit by writing a 1 to it.
1 = Intel® 6700PXH 64-bit PCI Hub receives a completion packet from the
PCI Express* interface from a previous request, and detects a data parity
error, and the Parity Error Response (PER) bit in the Command Register
(offset 04h, bit 6) is set.
7
RO
0
Fast Back-to-Back Transactions Capable (FBC): Does not apply to PCI
Express*. Hardwired to 0.
6
5
4
RO
RO
RO
0
0
1
Reserved.
66 MHz Enable (66EN): Does not apply to PCI Express*. Hardwired to 0.
Capabilities List (CAPL): Indicates that the Intel® 6700PXH 64-bit PCI Hub
contains the capabilities pointer in the bridge. Offset 34h (Capabilities List
Pointer - CAPP) indicates the offset for the first entry in the linked list of
capabilities. Default = 1.
86
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
