Signal Description
Figure 2-3. DWord Configuration Read Protocol (SMBus Word Write/Word Read,
PEC Enabled)
S
S
11X0_XXX
11X0_XXX
W
W
A
A
Cmd = 10010001
Cmd = 01010001
A
A
Bus Number
A
A
Device/Function
A
A
PEC
PEC
A P
CLOCK STRETCH
Register Num[7:0]
A P
Register Num[15:8]
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 10010001
Status
A
A
Sr
Data[31:24]
Data[15:8]
A
A
PEC
PEC
N
N
P
P
S
11X0_XXX
11X0_XXX
W
R
A
A
Cmd = 00010001
Data[23:16]
A
A
Sr
S
11X0_XXX
11X0_XXX
W
A
Cmd = 01010000
Data[7:0]
A
Sr
R
A
A
PEC
N P
Figure 2-4. DWord Configuration Read Protocol (SMBus Block Write/Block Read,
PEC Disabled)
S
11X0_XXX
W A
Cmd = 11000010
A
Byte Count = 4
A
Bus Number
A
Device/Function
A
Reg Number[15:8]
A
CLOCK
STRETCH
A
P
Reg Number [7:0]
S
11X0_XXX
11X0_XXX
W A
Cmd = 11000010
Byte Count = 5
A
A
N
P
Sr
A
Data[7:0]
R
A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
Figure 2-5. DWord Memory Read Protocol (SMBus Block Write/Block Read,
PEC Disabled)
CLOCK
STRETCH
S
11X0_XXX
W A
Cmd = 11100010
A
Byte Count = 4
A
Destination Mem
A
Add Offset[23:16]
A
Add Offset[15:8]
A
Add Offset[7:0]
A P
S
11X0_XXX
11X0_XXX
W A
Cmd = 11100010
Byte Count = 5
A
A
Sr
Data[7:0]
R
A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
A
N
P
Figure 2-6. DWord Configuration Read Protocol (SMBus Word Write/Word Read,
PEC Disabled)
S
S
1 1
1 1
X
X
0 _ X
0 _ X
X
X
X
X
W
W
A
A
C
m
d
=
1 0 0 0 0 0 0 1
A
A
B
u s
N
u
m
b e r
A
A
D
e
v ic e / F u n c t io
n
A
P
C
m
d
=
0 1 0 0 0 0 0
1
R
e
g is t e r u m [ 7 : 0 ]
N
C
L
O
C
K
S
T
R
E
T
C
H
A
P
R
e g is t e r
N
u m [ 1 5 : 8 ]
S
S
1 1
1 1
X
X
0 _ X
0 _ X
X
X
X
X
W
R
A
A
C
C
m
m
d
=
1 0 0 0 0 0 0 1
t a t u s
A
A
r
r
S
D
a t a [ 3 1 : 2 4
]
P
P
N
N
S
S
1 1 X
1 1
0
_ X
X
X
W
R
A
A
d
=
0 0 0 0 0 0 0 1
A
A
X
0 _ X
X
X
D
a t a [ 2 3 : 1 6 ]
D a t a [ 1 5 : 8 ]
S
S
1 1 X 0 _ X
1 1 X 0 _ X
X
X
W
A
C
m
d
=
0 1 0 0 0 0 0 0
A
r
X
X
R
A
D a t a [ 7 : 0 ]
P
N
2.16.4
Configuration and Memory Writes
Configuration and memory writes are accomplished through a series of SMBus writes. As with
reads, a write sequence is first used to initialize the Bus Number, Device, Function, and Register
Number for the configuration access and the destination memory, address offset for the memory
write. The writing of this information can be accomplished through any combination of the
supported SMBus write commands (Block, Word or Byte).
Intel® 6700PXH 64-bit PCI Hub Datasheet
67
INTEL [ INTEL ]
