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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
Figure 2-10. DWord Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC  
Enabled)  
S
S
11X0_XXX  
W
W
A
A
Cmd = 10110001  
Cmd = 01110001  
A
A
Dest Mem  
A
A
Add Offset[23:16]  
Add Offset[7:0]  
A
A
PEC  
PEC  
A P  
CLOCK STRETCH  
11X0_XXX  
A P  
Add Offset[15:8]  
S
11X0_XXX  
11X0_XXX  
W
R
A
A
Cmd = 10110001  
Status  
A
A
Sr  
Data[31:24]  
Data[15:8]  
A
A
PEC  
PEC  
N
N
P
P
S
11X0_XXX  
11X0_XXX  
W
R
A
A
Cmd = 00110001  
Data[23:16]  
A
A
Sr  
S
11X0_XXX  
11X0_XXX  
W
A
Cmd = 01110000  
Data[7:0]  
A
Sr  
R
A
A
PEC  
N P  
Figure 2-11. DWord Memory Read Protocol (SMBus Word Write/Byte Read, PEC  
Enabled)  
S
S
11X0_XXX  
11X0_XXX  
W
W
A
A
Cmd = 10110001  
Cmd = 01110001  
A
A
Dest Mem  
A
A
Add Offset[23:16]  
Add Offset[7:0]  
A
A
PEC  
PEC  
A
P
CLOCK STRETCH  
A
P
Add Offset[15:8]  
S
11X0_XXX  
11X0_XXX  
W
R
A
A
Cmd = 10110000  
Status  
A
A
Sr  
PEC  
PEC  
N
N
P
P
S
11X0_XXX  
11X0_XXX  
W
R
A
A
Cmd = 00110000  
Data[31:24]  
A
A
Sr  
S
11X0_XXX  
11X0_XXX  
W
A
Cmd = 00110000  
Data23:16]  
A
Sr  
R
A
A
PEC  
N P  
S
11X0_XXX  
11X0_XXX  
W
R
A
A
Cmd = 00110000  
Data15:8]  
A
A
Sr  
PEC  
PEC  
N
N
P
P
S
11X0_XXX  
11X0_XXX  
W
R
A
A
Cmd = 01110000  
Data[7:0]  
A
A
Sr  
2.16.5  
Error Handling  
The SMBus slave interface handles two types of errors: internal and PEC. Internal errors can occur  
for example when the SMBus tries to access the APIC or SHPC config/memory space and these  
units in Intel® 6700PXH 64-bit PCI Hub are stuck servicing a PCI Express* interface which is  
broken. Intel® 6700PXH 64-bit PCI Hub internally times out in such a case and this error  
manifests itself as a Not-Acknowledge (NACK) for the read or write command (End bit is set).  
Other internal errors include the read or write command receiving a master or target abort on the  
internal interface. If the master receives a NACK, the entire transaction should be reattempted.  
If the master supports packet error checking (PEC) and the PEC enable bit in the command is set,  
then the PEC byte is checked in the slave interface. If the check indicates a failure, then the slave  
will NACK the PEC packet and not issue the command on the internal interface.  
Note: An SMBus master must either do PEC on all transactions in a sequence or not do it at all i.e. it  
cannot turn on PEC in the middle of a sequence.  
Note: A PEC error in the middle of a sequence must be re-started from the beginning of the sequence i.e.  
the begin bit set.  
Intel® 6700PXH 64-bit PCI Hub Datasheet  
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