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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
2.16.6  
SMBus Interface Reset  
The master can reset the slave interface state machine in Intel® 6700PXH 64-bit PCI Hub in two  
ways:  
Τhe master holds SCL low for 25 ms cumulative. Cumulative in this case means that all the  
“low time” for SCL is counted between the Start and Stop bit. If this totals 25 ms before  
reaching the Stop bit, the interface is reset.  
Τhe master holds SCL continuously high for 50 ms.  
Besides these, the SMBus interface in Intel® 6700PXH 64-bit PCI Hub is also reset on a PWROK,  
RSTIN# or an in-band warm reset from PCI Express*.  
2.16.7  
Configuration Access Arbitration  
If the CPU is currently accessing a unit, SMBus cannot access it. Whoever gets in first wins  
arbitration. The other agent is stalled until the first agent finishes. The micro-architecture of this  
area is critical. The reason for the SMBus interface is to access registers when the system may be  
unstable or locked, which can result with broken queues. Any register access through SMBus must  
be able to proceed while the system is stuck.  
2.17  
System Setup  
2.17.1  
Clocking  
In addition to 33-MHz and 66-MHz PCI output clocking, the Intel® 6700PXH 64-bit PCI Hub  
requires 100-MHz and 133-MHz outputs to support PCI-X. Table 2-35 shows the Intel® 6700PXH  
64-bit PCI Hub clock domains.  
Table 2-35. Intel® 6700PXH 64-bit PCI Hub Clocking  
Clock Domain  
Frequency  
Source  
External  
Usage  
PCI Express*  
PCI  
100 MHz Differential  
133/100/66/33 MHz  
10-100KHz  
PCI Express* differential clocks.  
Internal  
PCI Bus. These only go to the external PCI Bus.  
SMBus  
Source  
Synchronous  
This pin is controlled by the driver of the SMBus  
interface, and will run between 10 and 100 kHz.  
TCK  
0-16 MHz  
External  
JTAG clock.  
70  
Intel® 6700PXH 64-bit PCI Hub Datasheet