Signal Description
2.16.3
Configuration And Memory Reads
Intel® 6700PXH 64-bit PCI Hub supports only read dword to internal register space. All
Configuration and memory reads are accomplished through an SMBus write(s) and later followed
by an SMBus read to read the status and the read data. For SMBus read transactions, the last byte
of data (or the PEC byte if enabled) is NACK’d by the master to indicate the end of the transaction.
The SMBus memory read command returns the status of the previous internal command and the
data associated previous internal read command. The status field encoding is shown in Table 2-34.
Table 2-34. SMBus Status Byte Encoding
Bit
Description
7
6
Internal Timeout: This bit is set if an SMBus request is not completed in 2 ms internally.
Reserved.
5
Internal Master Abort.
Internal Target Abort.
Reserved
4
3:1
0
Successful.
Examples of configuration and memory reads are shown in Figure 2-1 to Figure 2-6. For the
definition of the diagram conventions below, refer to the SMBus Specification, Revision 2.0.
Figure 2-1. DWord Configuration Read Protocol (SMBus Block Write/Block Read,
PEC Enabled)
S
11X0_XXX
W A
A
Cmd = 11010010
PEC
A
Byte Count = 4
A
Bus Number
A
Device/Function
A
Reg Number[15:8]
A
CLOCK
Reg Number [7:0]
A P
STRETCH
S
11X0_XXX
11X0_XXX
W A
Cmd = 11010010
Byte Count = 5
A
A
Sr
R
A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
N
P
A
Data[7:0]
A
PEC
Figure 2-2. DWord Memory Read Protocol (SMBus Block Write/Block Read,
PEC Enabled)
S
11X0_XXX
W A
Cmd = 11110010
A
Byte Count = 4
A
Destination Mem
A
Add Offset[23:16]
A
Add Offset[15:8]
A
CLOCK
STRETCH
PEC
A
P
Add Offset[7:0]
A
S
11X0_XXX
11X0_XXX
W A
Cmd = 11110010
Byte Count = 5
A
A
Sr
Data[7:0]
A
R
A
Status
A
Data[31:24]
A
Data[23:16]
A
Data[15:8]
A
PEC
N P
66
Intel® 6700PXH 64-bit PCI Hub Datasheet
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