Signal Description
Figure 2-12. Intel® 6700PXH 64-bit PCI Hub Clocking Diagram
The Intel® 6700PXH 64-bit PCI Hub component uses a 100-MHz differential pair clock inputs to
generate all of its core and PCI clocks. The differential clock inputs EXP_CLK and EXP_CLK#
are part of the PCI Express* interface. Board design must insure that all voltages supplying the
Intel® 6700PXH 64-bit PCI Hub (VCC, VCCEXP, VCC33 and VCC15) are valid before these PCI
Express* clocks begin running.
These clocks are fed into internal logic contained within the Intel® 6700PXH 64-bit PCI Hub to
generate a 2.5 GHz clock that runs the PCI Express* interface and the Intel® 6700PXH 64-bit PCI
Hub core. This 2.5 GHz clock is then fed into additional internal logic that converts the clock
frequency to one of the PCI/PCI-X supported frequencies (33/66/100/133 MHz for PCI or PCI-X).
Each of the PCI Bus segments supports 7 PCI output clocks, called PxPCLKO[6:0], where ‘x’ is
either and A or a B depending on which PCI Bus segment is being referenced. The PxPCLKO[6]
output clock is connected to the PCI feedback clock input PxPCLKI.
2.17.2
Component Reset
There are five types of reset that can be performed on the Intel® 6700PXH 64-bit PCI Hub. These
are listed from highest level of reset to the lowest level reset:
• PWROK – this signal indicates stable power when high and causes an asynchronous reset of
the entire Intel® 6700PXH 64-bit PCI Hub chip when low.
• RSTIN# – this is also an asynchronous reset to the Intel® 6700PXH 64-bit PCI Hub and can
be used for resetting the Intel® 6700PXH 64-bit PCI Hub for the front panel reset.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
