Signal Description
Table 2-33. SMBus Command Encoding (Sheet 2 of 2)
Bit
Description
3:2 Internal Command:
00 = Read DWord
01 = Write Byte
10 = Write Word
11 = Write DWord
All accesses are naturally aligned to the access width. This field specifies the internal command to be
issued by the SMBus slave logic to the Intel® 6700PXH 64-bit PCI Hub core.
1:0 SMBus Command:
00 = Byte
01 = Word
10 = Block
11 = Reserved
This field indicates the SMBus command to be issued on the SMBus interface. It is used as an indication
of the length of the transfer so that the slave knows when to expect the PEC packet (if enabled).
2.16.2
Initialization Sequence
All Configuration and memory read and writes are accomplished through SMBus write(s) and later
followed by an SMBus read (for a read command). The SMBus write sequence is used to initialize
the:
• Bus Number,
• Device/Function and
• 12-bit Register Number (in 2 separate bytes on SMBus)
for the configuration access. Each of the parameters above is sent on SMBus in separate bytes. The
register number parameter is initialized with two bytes and Intel® 6700PXH 64-bit PCI Hub
ignores the most significant 4 bits of the second byte that initializes the register number. For
memory reads and writes, the write sequence initializes the:
• Destination memory
• 24-bit memory address offset (in 3 separate bytes on SMBus)
The destination memory is a byte of information that indicates the internal memory space to access
in the Intel® 6700PXH 64-bit PCI Hub. The 24-bit address offset is used to address any internal
memory with up to an offset of 24 bits. The Intel® 6700PXH 64-bit PCI Hub only uses 12 bits of
address, and ignores the most significant 12 bits of the 24-bit address. The Intel® 6700PXH 64-bit
PCI Hub slave interface always expects 24 bits of address from the SMBus master though it uses
only 12 bits.
The initialization of the information can be accomplished through any combination of the
supported SMBus write commands (Block, Word or Byte). The Internal Command field for each
write should specify the same internal command every time (read or write). After all the
information is set up, the last write (End bit is set) initiates an internal read or write command. On
an internal read if the data is not available before the slave interface acknowledges this last write
command (ACK), the slave will “clock stretch” until the data returns to the SMBus interface unit.
On a internal write, if the write is not complete before the slave interface acknowledges this last
write command (ACK), the salve will “clock stretch” until the write completes internally. If an
error occurs (internal timeout, target or master abort on the internal switch) during the internal
access, the last write command will receive a NACK.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
