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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
Table 2-32. SMBus Address Configuration (Sheet 2 of 2)  
Bit  
Value  
2
1
SMBUS[2]  
SMBUS[1]  
The SMBus controller has access to all internal registers in the Intel® 6700PXH 64-bit PCI Hub. It  
can perform reads and writes from all registers through the particular interface’s configuration or  
memory space. I/OxAPIC memory space is accessible through its configuration space. SHPC  
memory space is directly accessible from the SMBus controller via the SMBus memory command.  
2.16.1  
SMBus Commands  
The Intel® 6700PXH 64-bit PCI Hub supports six SMBus commands:  
Block Write  
Block Read  
Word Write  
Word Read  
Byte Write  
Byte Read  
Sequencing these commands will initiate internal accesses to Intel® 6700PXH 64-bit PCI Hub’s  
configuration and memory registers. For high reliability, Intel® 6700PXH 64-bit PCI Hub also  
supports the optional Packet Error Checking feature (CRC-8) and is enabled or disabled with each  
transaction.  
Every configuration and memory read or write first consists of an SMBus write sequence which  
initializes the Bus Number, Device, function number, memory address offset etc. The term  
sequence is used since these variables can be initialized by the SMBus master with a single block  
write or multiple word or byte writes. The last write in the sequence that completes the  
initialization performs the internal configuration/memory read or write. The SMBus master can  
then initiate a read sequence which returns the status of the internal read or write command and  
also the data in case of a read.  
Each SMBus transaction has an 8-bit command driven by the master. The command encodes  
information as shown in Table 2-33.  
Table 2-33. SMBus Command Encoding (Sheet 1 of 2)  
Bit  
Description  
7
6
5
Begin: When set, this bit indicates the first transaction of the read or write sequence.  
End: When set, this bit indicates the last transaction of the read or write sequence.  
Memory/Configuration: This bit indicates whether memory or configuration space is being accessed in  
this SMBus sequence.  
1 = Memory Space  
0 = Configuration Space  
4
PEC Enable: When set, indicates PEC is enabled for the sequence. When enabled, each transaction in  
the sequence ends with an extra CRC byte. The Intel® 6700PXH 64-bit PCI Hub checks for CRC bytes  
on writes and generates CRC on reads.  
64  
Intel® 6700PXH 64-bit PCI Hub Datasheet