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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
Table 2-30. System Bus Delivery Address Format (Sheet 2 of 2)  
Bit  
Description  
11:4  
Enhanced Destination ID: This will be the same as bits 55:48 of the I/O Redirection Table entry for  
the interrupt associated with this message.  
3
Redirection Hint: This bit is used by the processor host bridge (system bus) to allow the interrupt  
message to be redirected.  
0 = The message will be delivered to the agent (processor) listed in bits 19:4.  
1 = The message will be delivered to an agent with a lower interrupt priority  
The Redirection Hint bit will be a 1 if bits 10:8 in the Delivery Mode field associated with  
corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit  
will be 0.  
2
Destination Mode: This bit is used only the Redirection Hint bit is set to 1. If the Redirection Hint bit  
and the Destination Mode bit are both set to 1, the logical destination mode is used, and the  
redirection is limited only to those processors that are part of the logical group as based on the  
logical ID.  
1:0  
00  
Table 2-31. System Bus Delivery Data Format  
Bit  
Description  
31:16  
15  
0000h  
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table for  
that interrupt.  
14  
Delivery Status: 1 = Assert, 0 = Deassert. If using edge-triggered interrupts, then bit will always be  
1, since only the assertion is sent. If using level-triggered interrupts, then this bit indicates the state  
of the interrupt input.  
13:12  
11  
00  
Destination Mode: 1 = Logical, 0 = Physical. Same as the corresponding bit in the Redirection  
Table  
10:8  
7:0  
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that  
interrupt.  
Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.  
2.16  
SMBus Interface  
The SMBus address is set upon PWROK by sampling SMBUS[5] and SMBUS[3:1]. When the  
pins are sampled, the resulting Intel® 6700PXH 64-bit PCI Hub SMBus address is shown in  
Table 2-32.  
Table 2-32. SMBus Address Configuration (Sheet 1 of 2)  
Bit  
Value  
7
6
5
4
3
1
1
SMBUS[5]  
0
SMBUS[3]  
Intel® 6700PXH 64-bit PCI Hub Datasheet  
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