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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
signal that represents the logical OR of all of the Intel® 6700PXH 64-bit PCI Hub’s interrupt pins.  
The logical OR’ing includes both PCI sides A and B for the Intel® 6700PXH 64-bit PCI Hub. The  
DEASSERT message captures the deasserting edge of the signal that represents the logical OR of  
all of the Intel® 6700PXH 64-bit PCI Hub’s interrupt pins.  
Table 2-29. Intel® 6700PXH 64-bit PCI Hub INTx Routing  
PCI Interrupt Pins  
Internal Interrupts  
PCI Express* INTx Message  
0, 4, 8, 12  
1, 5, 9, 13  
2, 6, 10, 14  
3, 7, 11, 15  
SHPC A (IRQ[23])  
INTA  
INTB  
INTC  
INTD  
SHPC B  
-
-
2.15.3  
2.15.4  
Buffer Flushing  
The Intel® 6700PXH 64-bit PCI Hub does not implement any buffer flushing features. When the  
Intel® 6700PXH 64-bit PCI Hub receives an interrupt on its interrupt pin, it does not flush its  
posted write buffers in the inbound direction in the PCI interface. This is not required from the  
Intel® 6700PXH 64-bit PCI Hub because PCI device drivers ultimately have to guarantee that all  
posted writes from the device to the memory are all flushed before executing the interrupt service  
routine.  
EOI Special Cycles  
The Intel® 6700PXH 64-bit PCI Hub can receive EOI special cycles over PCI Express* in the  
IA32 processor system bus mode. This is the result of the MCH broadcasting the IA32 processor  
system bus EOI cycle. Both I/OxAPICs in the Intel® 6700PXH 64-bit PCI Hub would compare the  
vector number in the EOI data field with the vector field for each entry in the I/O Redirection  
Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry in the I/OxAPIC  
will be cleared. The Intel® 6700PXH 64-bit PCI Hub does not forward the EOI to the PCI bus.  
Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one  
interrupt input, each of those entries will have the Remote_IRR bit reset to '0'.  
2.15.5  
Interrupt Delivery  
The Intel® 6700PXH 64-bit PCI Hub I/OxAPIC can deliver interrupts to the processor through the  
system bus (via the PCI Express* interface).  
When an interrupt message needs to be sent over the PCI Express* bus, i.e. when the IRR bit is set  
for an interrupt, the Intel® 6700PXH 64-bit PCI Hub will perform a memory write on the PCI  
Express* bus, as seen in Table 2-30 and Table 2-31.  
Table 2-30. System Bus Delivery Address Format (Sheet 1 of 2)  
Bit  
Description  
31:20 FEEh  
19:12 Destination ID: This will be the same as bits [63:56] of the I/O Redirection Table entry for the  
interrupt associated with this message.  
62  
Intel® 6700PXH 64-bit PCI Hub Datasheet