Signal Description
2.15
I/OxAPIC Interrupt Controller (Functions 1 and 3)
The Intel® 6700PXH 64-bit PCI Hub contains two I/OxAPIC controllers, both of which reside on
the primary bus. The intended use of these controllers on the Intel® 6700PXH 64-bit PCI Hub is to
have the interrupts from PCI bus A connected to the interrupt controller on function 1, and have the
interrupts on PCI bus B connected to the interrupt controller on function 3.
2.15.1
Interrupt Support
The Intel® 6700PXH 64-bit PCI Hub behaves as a normal peer-to-peer bridge and can handle PCI
IRQ# and PCI MSI system interrupt mechanisms.
2.15.1.1
PCI IRQ# Interrupts
The Intel® 6700PXH 64-bit PCI Hub can manage 16 pin interrupts, and has 16 pins (PxIRQ#) for
these interrupts. Interrupts delivered by a pin can be either in level or edge mode, and may be either
active high or active low. Since this I/OxAPIC is connected to a PCI bus, its most likely
configuration will be as active low level, which will match the PCI pin polarity and functionality.
Each pin is collected by the Intel® 6700PXH 64-bit PCI Hub, synchronized into the PCI clock
domain, and scheduled for delivery if it is unmasked.
The Intel® 6700PXH 64-bit PCI Hub only has 16 interrupt pins per PCI segment. These pins are
connected to I/OxAPIC redirection table entries 15 – 0 (of 24 entries). The standard hot plug
controller is hard-wired to redirection table entry 23 of the I/OxAPIC. All other interrupts are only
addressable through the PCI virtual wire mechanism. If PxIRQ[12:11]# are unused, they must be
pulled up to VCC33 to ensure the boot interrupt works correctly. All other IRQ pins are terminated
on-die.
2.15.1.2
PCI Message Signaled Interrupts (MSI)
These interrupts which appear on the PCI bus as inbound memory writes are decoded by the
Intel® 6700PXH 64-bit PCI Hub in the PCI bridge inverse decode window and passed upstream
without any modifications. BIOS would setup the PCI bridge decode register such that
0xFEEx_xxxx falls in the inverse decode window of the Intel® 6700PXH 64-bit PCI Hub.
2.15.2
PCI Express* Legacy INTx Support and Boot Interrupt
The Intel® 6700PXH 64-bit PCI Hub has the capability to generate an in-band interrupt request on
the PCI Express* bus when the APIC is disabled. This in-band interrupt mechanism is necessary
for systems that do not support the APIC and for boot. The PCI Express* protocol describes an in-
band legacy wire-interrupt INTx mechanism for I/O devices to signal PCI-style level interrupts.
The Intel® 6700PXH 64-bit PCI Hub generates a PCI Express* INTx message as follows: each
interrupt pin input (16 interrupt pins) and INT[23]# is compared with its mask (bit 16 in the
redirection table low, RDL register). If the interrupt is masked in the Intel® 6700PXH 64-bit PCI
Hub APIC, that interrupt needs to cause an INTx message over the PCI Express* bus whenever
asserted. If the interrupt is not masked, then that interrupt is being used by the Intel® 6700PXH
64-bit PCI Hub APIC and should not cause an INTx message on the PCI Express* bus.
In the PCI Express* protocol, boot interrupts are virtualized using a pair of ASSERT and
DEASSERT messages. This then gives a way to preserve the level-sensitive semantics of the PCI
interrupts on the PCI Express* bus. The ASSERT message will capture the asserting edge of the
Intel® 6700PXH 64-bit PCI Hub Datasheet
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