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6700PXH 参数 Datasheet PDF下载

6700PXH图片预览
型号: 6700PXH
PDF下载: 下载PDF文件 查看货源
内容描述: 64位PCI中枢 [64-bit PCI Hub]
分类和应用: PC
文件页数/大小: 194 页 / 2283 K
品牌: INTEL [ INTEL ]
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Signal Description  
Accesses to the internal Intel® 6700PXH 64-bit PCI Hub configuration registers, which includes  
the bridge configuration registers and the CSR memory registers, follow no ordering relationship  
with respect to transactions moving to and from the PCI and PCI Express* buses. Outbound  
memory/configuration transactions to the internal register space could complete out of order with  
respect to transactions pending in the outbound queues towards the PCI bus. Software must be  
aware that any semaphore mechanism implemented through the internal Intel® 6700PXH 64-bit  
PCI Hub register space requires a dummy read to PCI or PCI Express* space to push the writes that  
could be pending in the Intel® 6700PXH 64-bit PCI Hub queues in either direction. The ordering  
tables in the next two sections do not consider these transactions.  
2.14.1.1  
Inbound Transaction Ordering  
Table 2-27 lists the combined set of ordering rules in the inbound path of the Intel® 6700PXH  
64-bit PCI Hub.  
Table 2-27. Inbound Transaction Ordering  
Delayed/Split  
Read  
Completion  
Delayed/Split  
Write  
Completion  
Posted  
Write  
Delayed/Split  
Read Request  
Row pass Column  
Posted Write  
No  
No  
Yes  
Yes  
No  
No  
No  
Delayed/Split Read  
Request  
Yes  
Delayed/SplitIO Write  
Request  
No  
No  
No  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
NO  
No  
Delayed/Split Read  
Completion  
Delayed/Split  
Write Completion  
2.14.1.2  
Outbound Transaction Ordering  
Table 2-28 lists the combined set of ordering rules in the outbound path of the Intel® 6700PXH  
64-bit PCI Hub.  
Table 2-28. Outbound Transaction Ordering  
Delayed  
(Split) Read  
Request  
Delayed (Split)  
Read  
Completion  
Delayed (Split)  
Write  
Completion  
Posted  
Write  
Row pass Column  
Posted Write  
No  
No  
Yes  
Yes  
Yes  
Yes  
Yes  
Delayed/Split Read  
Request  
Yes1  
Delayed/Split  
Write Request  
No  
Yes  
Yes  
Yes  
Delayed/SplitIO Write  
Completion  
No  
No  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Delayed/Split  
Read Completion  
NOTE: The Intel® 6700PXH 64-bit PCI Hub supports two outbound completion required requests per PCI  
segment. Outbound delayed/split read requests can pass each other when issued on the PCI bus.  
60  
Intel® 6700PXH 64-bit PCI Hub Datasheet