Signal Description
2.13.2.1.18 Memory Accesses to I/OxAPIC and SHPC Memory Space
Memory accesses to I/OxAPIC memory space are handled through two address ranges and an
access enable bit in I/OxAPIC configuration space, as follows:
• A 32-bit BAR (MBAR)
• An alternate 32-bit BAR (ABAR)
• Memory space enable bit (MSE) in the Command register
Refer to the chapter on I/OxAPIC for more details about these BARs. Memory accesses to SHPC
memory space are handled through a 64-bit and an access enable bit:
• A 64-bit BAR (SHPC_BAR)
• Memory space enable bit (MSE) in the Command register
2.13.3
VGA Addressing
2.13.3.1
Mode Access Mechanism
When a VGA-compatible device exists behind a Intel® 6700PXH 64-bit PCI Hub bridge, the VGA
Enable bit (bit 3) in the Bridge Control Register must be set (offset 3E–3Fh). If this bit is set, the
Intel® 6700PXH 64-bit PCI Hub forwards all transactions addressing the VGA frame buffer
memory and VGA I/O registers from the PCI Express* interface to PCI, regardless of the values of
the Intel® 6700PXH 64-bit PCI Hub base and limit address registers. The Intel® 6700PXH 64-bit
PCI Hub will not forward VGA frame buffer memory accesses to the PCI Express* interface
regardless of the values of the memory address ranges. However, the I/O Enable and Memory
Enable bits in the PD_CMD Register must still be set. When the bit is cleared, the Intel® 6700PXH
64-bit PCI Hub forwards transactions addressing the VGA frame buffer memory and VGA I/O
registers from PCI Express* to PCI if the defined memory address ranges enable forwarding. All
accesses to the VGA frame buffer memory are forwarded from the PCI bus to the PCI Express*
interface if the defined memory address ranges enable forwarding. However, the master enable bit
must still be set. The VGA I/O addresses are never forwarded to the PCI Express* interface.
The VGA frame buffer consists of the following memory address range: 000A 0000h–00B FFFFh
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh. These I/O
addresses are aliased every 1 Kbyte throughout the first 64 Kbytes of I/O space. This means that
address bits [9:0] (3B0h–3BBh and 3C0h–3DFh) are decoded, [15:10] are not decoded and can be
any value, and address bits [31:16] must be all 0s.
2.14
Transaction Ordering
2.14.1
Intel® 6700PXH 64-bit PCI Hub Transaction Ordering
The Intel® 6700PXH 64-bit PCI Hub follows the producer-consumer model of a standard PCI
Express*-PCI bridge. Based on this model, the Intel® 6700PXH 64-bit PCI Hub implements a set
of ordering rules in the inbound and outbound directions. The ordering plane covered by these rules
spans the transaction domain covered by PCI Express* and either of the two PCI segments. The
Intel® 6700PXH 64-bit PCI Hub uses a single PCI Express* virtual channel for both PCI segments
to communicate with the MCH.
Intel® 6700PXH 64-bit PCI Hub Datasheet
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INTEL [ INTEL ]
