Signal Description
2.13.2.1.16 Memory Base and Limit Address Registers
The Memory Base Address and Memory Limit Address Registers define an address range that the
Intel® 6700PXH 64-bit PCI Hub uses to determine when to forward memory commands. The
Intel® 6700PXH 64-bit PCI Hub forwards a memory transaction from the PCI Express* interface
to the PCI bus if the address falls within the range, and forwards it from the PCI bus to the PCI
Express* interface or the peer bridge if the address is outside the range (provided that they do not
fall into the prefetchable memory range. This memory range supports 32-bit addressing only
(addresses 4 Gbytes) and supports 1-Mbyte granularity and alignment.
This range is defined by a 16-bit base address register at offset 20h in configuration space and a
16-bit limit address register at offset 22h. The top 12 bits of each of these registers correspond to
bits [31:20] of the memory address. The low 4 bits are hardwired to ground. The low 20 bits of the
base address are assumed to be all 0s, which results in a natural alignment to a 1-Mbyte boundary.
The low 20 bits of the limit address are assumed to be all 1s, which results in an alignment to the
top of a 1-Mbyte block.
Note: Setting the base to a value greater than that of the limit turns off the memory range.
2.13.2.1.17 Prefetchable Memory Base and Limit Address Registers, Upper 32-bit
Registers
The prefetchable memory base and address registers, along with their upper 32-bit counterparts,
define an additional address range that the Intel® 6700PXH 64-bit PCI Hub uses to forward
accesses. The Intel® 6700PXH 64-bit PCI Hub forwards a memory transaction from the PCI
Express* interface to PCI if the address falls within the range, and forwards transactions from PCI
to the PCI Express* interface (or the peer bridge) if the address is outside the range and do not fall
into the regular memory range. This memory range supports 64-bit addressing, and supports
1-Mbyte granularity and alignment.
This lower 32-bits of the range are defined by a 16-bit base register at offset 24h in configuration
space and a 16-bit limit register at offset 28h. The top 12 bits of each of these registers correspond
to bits [31:20] of the memory address. The low 4 bits are hardwired to VCC, indicating 64-bit
address support. The low 20 bits of the base address are assumed to be all 0s, which results in a
natural alignment to a 1-Mbyte boundary. The low 20 bits of the limit address are assumed to be all
1s, which results in an alignment to the top of a 1-Mbyte block.
The upper 32-bits of the range are defined by a 32-bit base register at offset 28h in configuration
space, and a 32-bit limit register at offset 2Ch.
Note: Setting the entire base (with upper 32-bits) to a value greater than that of the limit turns off the
memory range.
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Intel® 6700PXH 64-bit PCI Hub Datasheet
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