Register Description
Bits
Type
Reset
Description
1
0
RWS
RWS
0
0
Master-Abort on Split Completion Mask (MASCM)
Target-Abort on Split Completion Mask (TASCM)
3.6.1.11
Offset 134h: UNC_PXERRSEV – Uncorrectable
PCI/PCI-X Error Severity Register (D0:F0, F2)
Offset:
Default Value: 2340h
134 – 135h
Attribute: RWS, RO
Size: 16 bits
This register controls whether an individual PCI-X uncorrectable error is reported as a fatal or non-
fatal error. A PCI-X uncorrectable error, if enabled, is reported as fatal (an ERR_FATAL message
will be generated on the PCI Express* bus) when the corresponding error bit in the severity register
is set to a 1. If a bit is set to 0, then the corresponding error, if enabled, is considered non-fatal (and
thus a ERR_NONFATAL message will be generated on the PCI Express* bus). There is one mask
bit per error.
Bits
Type
Reset
Description
15:14
13
12
11
10
9
RO
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
Reserved.
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
Internal Bridge Error Severity (IBES)
SERR# Assertion Severity (SEAS)
PERR# Assertion Severity (PEAS)
Delayed Transaction Timer Expired Severity (DTTES)
Uncorrectable Address Error Severity (UADDES)
Uncorrectable Attribute Error Severity (UATTES)
Uncorrectable Data Error Severity (UDES)
Uncorrectable Split Completion Message Data Error Severity (USCMDES)
Unexpected Split Completion Error Severity (USCES)
Reserved.
8
7
6
5
4
3
Master-Abort Severity (MAS)
2
Received Target-Abort Severity (RTAS)
Master-Abort on Split Completion Severity (MASCS)
Target-Abort on Split Completion Severity (TASCS)
1
0
Intel® 6700PXH 64-bit PCI Hub Datasheet
121
INTEL [ INTEL ]
