Register Description
3.6.1.9
Offset 12Ch: UNC_PXERRSTS – Uncorrectable
PCI/PCI-X Error Status Register (D0:F0, F2)
Offset:
Default Value: 0000h
12C – 12Dh
Attribute: RWCS, RO
Size: 16 bits
This register reports error status of individual errors generated on the PCI or PCI-X secondary bus
interface. An individual error status bit that is set to a 1 indicates that a particular error occurred;
software may clear an error status by writing a 1 to the respective bit. Refer to Chapter 10 of the
PCI Express* to PCI/PCI-X Bridge Specification Revision 1.0 for more details.
Bits
Type
Reset
Description
15:14
13
RO
0
0
Reserved.
RWCS
Internal Bridge Error (IBERR): Accounts for internal data errors in the Intel®
6700PXH 64-bit PCI Hub’s data queues in either direction. The Intel®
6700PXH 64-bit PCI Hub does NOT log any headers for this error.
12
11
RWCS
RWCS
0
0
SERR# Assertion Detected (SERRAD): The Intel® 6700PXH 64-bit PCI Hub
sets this bit whenever it detects the PCI PxSERR# pin is asserted. There is no
header logging associated with the setting of this bit.
PERR# Assertion Detected (PERRAD): The Intel® 6700PXH 64-bit PCI Hub
sets this bit whenever it detects the PCI bus PxPERR# pin asserted when it is
mastering a write (memory, I/O or configuration) or a split/delayed read
completion on the PCI bus. The Intel® 6700PXH 64-bit PCI Hub logs the
header of the transaction in which the PxPERR# was detected (regardless of
the data phase in which it is detected), in the PCI-X header log register.
Note that this status bit and also the associated header log are always done
irrespective of whether the PxPERR# detected was because of a PCI bus error
or because of a forwarded poisoned data. But error message escalation to PCI
Express* is done only if the PxPERR# detected and was a NOT because of
forwarded poisoned data.
10
9
RWCS
RWCS
0
0
Delayed Transaction Timer Expired (DTTE): This bit is set by the Intel®
6700PXH 64-bit PCI Hub if it detects that a DT timeout has happened on a
hard DT read stream or on an inbound I/O or configuration transaction. No
header is logged.
Uncorrectable Address Error Detected (UADED): The Intel® 6700PXH
64-bit PCI Hub sets this bit when it is the target of an inbound transaction and
an address parity error was detected by the Intel® 6700PXH 64-bit PCI Hub
(regardless of whether the bus mode is PCI or PCI-X Mode 1). The Intel®
6700PXH 64-bit PCI Hub logs the header of the transaction in which it detected
the address/attribute parity error in the PCI-X header log register.
8
7
RWCS
RWCS
0
0
Uncorrectable Attribute Error Detected (UATED): The Intel® 6700PXH
64-bit PCI Hub sets this bit when it is the target of an inbound transaction and
an attribute parity error was detected by the Intel® 6700PXH 64-bit PCI Hub
(regardless of whether the bus mode is PCI-X Mode 1). The Intel® 6700PXH
64-bit PCI Hub logs the header of the transaction in which it detected the
address/attribute parity error in the PCI-X header log register.
Uncorrectable Data Error Detected (UDED): The Intel® 6700PXH 64-bit PCI
Hub sets this bit in all PCI modes (PCI, PCI-X Mode 1) when it is the target of
an inbound transaction or when it is mastering a PCI delayed read with target
sourcing data to the Intel® 6700PXH 64-bit PCI Hub, and a data parity error
was detected by the Intel® 6700PXH 64-bit PCI Hub. The Intel® 6700PXH
64-bit PCI Hub logs the header of the transaction in which it detected the data
parity error in the PCI-X header log register.
6
RWCS
0
Uncorrectable Split Completion Message Data Error (USCMDE): This bit is
set when a split completion message is received with an uncorrectable data
parity error.
Intel® 6700PXH 64-bit PCI Hub Datasheet
119
INTEL [ INTEL ]
