Register Description
3.6.1.16
Offset 170h: PXH_STPSTS – Intel® 6700PXH
64-bit PCI Hub Strap Status Register (D0:F0, F2)
Offset:
Default Value: xxxxh
170 – 171h
Attribute: RO
Size: 16 bits
This register indicates the status of various Power-On straps on the Intel® 6700PXH 64-bit PCI
Hub.
Bits
Type
Reset
Description
15
14
RO
RO
RO
RO
0
Reserved.
Reserved.
Strap
0
13:12
11:8
Reserved.
Strap
PCI Slot Count (PSC): Reflects the value of the HPxSLOT[3:0]# pins sampled
at the rising edge of PWROK.
7:1
RO
Strap
Manageability Address (MA): These 7 bits represent the address the SMBus
slave port will respond to when an access is attempted. This register will have
the following value:
Bit Value
7
6
5
4
3
2
1
‘1’
‘1’
SMBUS[7]
‘0’
SMBUS[6]
SMBUS[5]
SMBUS[4]
0
RO
Strap
P133EN Status (133EN_STS): Reflects the status of the Px133EN pin
sampled at rising edge of PWROK.
3.6.2
Power Management Registers
This configuration space follows the standard PCI-to-PCI bridge configuration space format.
Table 3-2 shows the Intel® 6700PXH 64-bit PCI Hub power management registers and their
address byte offset values.
Note: Registers that are not shown should be treated as Reserved.
Table 3-2. Power Management Register Summary
Address
Offset
Symbol
Register Name
Default
Access
300–303h
PWR_BUDCAP
Power Budgeting Enhanced
Capability Register
00010004h
RO
304h
PWR_DATASEL
Power Budgeting Data Select
Register
00h
RW
308–30Bh
30C–30Dh
314h–...
PWR_DATAREG Power Budgeting Data Register
00000000h
0000h
RO
PWR_BUDREG
PWR_BUDREG0
Power Budgeting Register
RWO
Power Budgeting Register 0...
0000h
RO, RW
Intel® 6700PXH 64-bit PCI Hub Datasheet
125
INTEL [ INTEL ]
