Register Description
Bits
Type
Reset
Description
5
RWCS
0
Unexpected Split Completion Error (USCE): This bit is set when a
completion is received from PCI-X that matches the bus number range on the
primary side of the Intel® 6700PXH 64-bit PCI Hub, but the RequestorID:tag
combination does not match one of the non-posted transactions that Intel®
6700PXH 64-bit PCI Hub has outstanding on the PCI-X bus.
4
3
RO
0
0
Reserved.
RWCS
Master-Abort Status (MAS): The Intel® 6700PXH 64-bit PCI Hub sets this bit
when it is the master of a request transaction on the PCI bus and it received a
master abort. The header is logged for that transaction.
2
1
RWCS
RWCS
0
0
Received Target-Abort Status (RTAS): The Intel® 6700PXH 64-bit PCI Hub
sets this bit when it is the master of a request transaction on the PCI bus and it
received a target abort. The header is logged for that transaction.
Master-Abort on Split Completion Status (MA_SCS): The Intel® 6700PXH
64-bit PCI Hub sets this bit when a split completion it sends on the PCI-X bus
master aborts. The Intel® 6700PXH 64-bit PCI Hub logs the header of the split
completion.
0
RWCS
0
Target-Abort on Split Completion Status (TA_SCS): The Intel® 6700PXH
64-bit PCI Hub sets this bit when a split completion it sends on the PCI-X bus
target aborts. The Intel® 6700PXH 64-bit PCI Hub logs the header.
3.6.1.10
Offset 130h: UNC_PXERRMSK – Uncorrectable
PCI/PCI-X Error Mask Register (D0:F0, F2)
Offset:
Default Value: 000017A8h
130 – 133h
Attribute: RWS, RO
Size: 32 bits
This register masks the reporting of individual PCI-X uncorrectable errors via a PCI Express* error
message. There is one mask bit per error. Note that the status bits are set in the status register
irrespective of whether the mask bit is on or off. The mask bit also affects the header log for the
PCI-X transaction. If the mask bit is on, the header is not logged and no error message is generated
on the PCI Express* bus.
Bits
Type
Reset
Description
31:14
13
12
11
10
9
RO
0
0
1
0
1
1
1
1
0
1
0
1
0
Reserved.
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RWS
RO
Internal Bridge Error (IBE)
SERR# Assertion Mask (SEAM)
PERR# Assertion Mask (PEAM)
Delayed Transaction Timer Expired Mask (DTTEM)
Uncorrectable Address Error Mask (UADDEM)
Uncorrectable Attribute Error Mask (UATTEM)
Uncorrectable Data Error Mask (UDEM)
Uncorrectable Split Completion Message Data Error (USCMDE)
Unexpected Split Completion Error (USCE)
Reserved.
8
7
6
5
4
3
RWS
RWS
Master-Abort Mask (MAM)
2
Received Target-Abort Mask (RTAM)
120
Intel® 6700PXH 64-bit PCI Hub Datasheet
INTEL [ INTEL ]
